WRPLL gateware
kasli_soc: add wrpll, and its IRQs for satellite ddmtd: add ddmtd and deglitcher ddmtd: add phase and period collector wrpll: add helper clockdomain wrpll: add frequency counter wrpll: add gtx_period, gtx_tag and main_tag csr wrpll: move collector result from helper CD to sys CD and CSR wrpll: add phase & period eventmanage for shared peripheral interrupt
This commit is contained in:
parent
e08d942066
commit
0cd1ac9204
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@ -0,0 +1,156 @@
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from migen import *
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from migen.genlib.cdc import PulseSynchronizer, MultiReg
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from migen.genlib.fsm import FSM
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from misoc.interconnect.csr import *
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class DDMTDSamplerGTX(Module):
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def __init__(self, gtx, main_xo_pads):
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self.gtx_beating = Signal()
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self.main_beating = Signal()
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# # #
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main_clk_se = Signal()
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gtx_beating_FF = Signal()
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main_beating_FF = Signal()
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self.specials += [
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Instance("IBUFDS",
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i_I=main_xo_pads.p, i_IB=main_xo_pads.n,
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o_O=main_clk_se),
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# Two back to back FFs are used to prevent metastability
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Instance("FD", i_C=ClockSignal("helper"),
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i_D=gtx.cd_rtio_rx0.clk, o_Q=gtx_beating_FF),
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Instance("FD", i_C=ClockSignal("helper"),
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i_D=gtx_beating_FF, o_Q=self.gtx_beating),
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Instance("FD", i_C=ClockSignal("helper"),
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i_D=main_clk_se, o_Q=main_beating_FF,),
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Instance("FD", i_C=ClockSignal("helper"),
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i_D=main_beating_FF, o_Q=self.main_beating,)
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]
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class DDMTDDeglitcherFirstEdge(Module):
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def __init__(self, input_signal, blind_period=128):
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self.detect = Signal()
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rising = Signal()
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input_signal_r = Signal()
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# # #
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self.sync.helper += [
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input_signal_r.eq(input_signal),
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rising.eq(input_signal & ~input_signal_r)
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]
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blind_counter = Signal(max=blind_period)
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self.sync.helper += [
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If(blind_counter != 0, blind_counter.eq(blind_counter - 1)),
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If(input_signal_r, blind_counter.eq(blind_period - 1)),
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self.detect.eq(rising & (blind_counter == 0))
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]
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class DDMTD(Module):
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def __init__(self, counter, input_signal):
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# in helper clock domain
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self.h_tag = Signal(len(counter))
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self.h_tag_update = Signal()
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# # #
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deglitcher = DDMTDDeglitcherFirstEdge(input_signal)
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self.submodules += deglitcher
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self.sync.helper += [
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self.h_tag_update.eq(0),
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If(deglitcher.detect,
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self.h_tag_update.eq(1),
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self.h_tag.eq(counter)
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)
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]
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class Collector(Module):
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"""
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A phase and period collector for DDMTD
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"""
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def __init__(self, N):
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self.gtx_stb = Signal()
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self.main_stb = Signal()
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self.tag_gtx = Signal(N)
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self.tag_main = Signal(N)
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self.out_period_stb = Signal()
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self.out_beating_period = Signal(N)
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last_gtx_tag = Signal(N)
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beating_period_r = Signal(N)
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self.out_phase_stb = Signal()
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self.out_tag_gtx = Signal(N)
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self.out_tag_main = Signal(N)
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tag_gtx_r = Signal(N)
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tag_main_r = Signal(N)
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# # #
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# Period collector
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# collect the difference between each gtx tags
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self.submodules.period_colr_fsm = period_colr_fsm = FSM(reset_state="IDLE")
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period_colr_fsm.act("IDLE",
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NextValue(self.out_period_stb, 0),
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If(self.gtx_stb,
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NextValue(beating_period_r, self.tag_gtx - last_gtx_tag),
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NextValue(last_gtx_tag, self.tag_gtx),
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NextState("OUTPUT")
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)
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)
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period_colr_fsm.act("OUTPUT",
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NextValue(self.out_beating_period, beating_period_r),
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NextValue(self.out_period_stb, 1),
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NextState("IDLE")
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)
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# Phase collector
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# collect main and gtx tag
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self.submodules.phase_colr_fsm = phase_colr_fsm = FSM(reset_state="IDLE")
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phase_colr_fsm.act("IDLE",
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NextValue(self.out_phase_stb, 0),
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If(self.gtx_stb & self.main_stb,
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NextValue(tag_gtx_r, self.tag_gtx),
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NextValue(tag_main_r, self.tag_main),
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NextState("OUTPUT")
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).Elif(self.gtx_stb,
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NextValue(tag_gtx_r, self.tag_gtx),
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NextState("WAITMAIN")
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).Elif(self.main_stb,
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NextValue(tag_main_r, self.tag_main),
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NextState("WAITGTX")
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)
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)
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phase_colr_fsm.act("WAITGTX",
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If(self.gtx_stb,
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NextValue(tag_gtx_r, self.tag_gtx),
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NextState("OUTPUT")
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)
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)
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phase_colr_fsm.act("WAITMAIN",
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If(self.main_stb,
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NextValue(tag_main_r, self.tag_main),
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NextState("OUTPUT")
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)
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)
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phase_colr_fsm.act("OUTPUT",
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NextValue(self.out_tag_gtx, tag_gtx_r),
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NextValue(self.out_tag_main, tag_main_r),
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NextValue(self.out_phase_stb, 1),
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NextState("IDLE")
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)
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@ -26,6 +26,7 @@ import analyzer
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import acpki
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import acpki
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import drtio_aux_controller
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import drtio_aux_controller
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import zynq_clocking
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import zynq_clocking
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import wrpll
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import si549
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import si549
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from config import write_csr_file, write_mem_file, write_rustc_cfg_file
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from config import write_csr_file, write_mem_file, write_rustc_cfg_file
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@ -564,6 +565,17 @@ class GenericSatellite(SoCCore):
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else:
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else:
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self.submodules.main_dcxo = si549.Si549(platform.request("ddmtd_main_dcxo_i2c"))
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self.submodules.main_dcxo = si549.Si549(platform.request("ddmtd_main_dcxo_i2c"))
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self.submodules.helper_dcxo = si549.Si549(platform.request("ddmtd_helper_dcxo_i2c"))
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self.submodules.helper_dcxo = si549.Si549(platform.request("ddmtd_helper_dcxo_i2c"))
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self.submodules.wrpll = wrpll.WRPLL(
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gtx=self.gt_drtio,
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main_dcxo_pads=platform.request("cdr_clk_clean_fabric"),
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helper_dcxo_pads=platform.request("ddmtd_helper_clk"))
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self.csr_devices.append("main_dcxo")
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self.csr_devices.append("helper_dcxo")
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self.csr_devices.append("wrpll")
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self.comb += [
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self.ps7.interrupt[0].eq(self.wrpll.period_ev.irq), # IRQ_ID = 61
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self.ps7.interrupt[1].eq(self.wrpll.phase_ev.irq) # IRQ_ID = 62
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]
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self.config["HAS_SI549"] = None
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self.config["HAS_SI549"] = None
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gtx0 = self.gt_drtio.gtxs[0]
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gtx0 = self.gt_drtio.gtxs[0]
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@ -0,0 +1,140 @@
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from migen import *
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from migen.genlib.cdc import MultiReg, AsyncResetSynchronizer, PulseSynchronizer
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from misoc.interconnect.csr import *
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from misoc.interconnect.csr_eventmanager import *
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from ddmtd import DDMTDSamplerGTX, DDMTD, Collector
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class FrequencyCounter(Module, AutoCSR):
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def __init__(self, counter_width=24, domains=["gtx0_rtio_rx", "sys", "helper"]):
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for domain in domains:
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name = "counter_" + domain
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counter = CSRStatus(counter_width, name=name)
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setattr(self, name, counter)
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self.update_en = CSRStorage()
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timer = Signal(counter_width)
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timer_tick = Signal()
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self.sync += Cat(timer, timer_tick).eq(timer + 1)
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for domain in domains:
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sync_domain = getattr(self.sync, domain)
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divider = Signal(2)
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sync_domain += divider.eq(divider + 1)
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divided = Signal()
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divided.attr.add("no_retiming")
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sync_domain += divided.eq(divider[-1])
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divided_sys = Signal()
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self.specials += MultiReg(divided, divided_sys)
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divided_sys_r = Signal()
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divided_tick = Signal()
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self.sync += divided_sys_r.eq(divided_sys)
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self.comb += divided_tick.eq(divided_sys & ~divided_sys_r)
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counter = Signal(counter_width)
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counter_csr = getattr(self, "counter_" + domain)
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self.sync += [
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If(timer_tick,
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If(self.update_en.storage, counter_csr.status.eq(counter)),
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counter.eq(0),
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).Else(
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If(divided_tick, counter.eq(counter + 1))
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)
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]
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class WRPLL(Module, AutoCSR):
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def __init__(self, gtx, main_dcxo_pads, helper_dcxo_pads, COUNTER_BIT=32):
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self.gtx_period = CSRStatus(COUNTER_BIT)
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self.gtx_tag = CSRStatus(COUNTER_BIT)
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self.main_tag = CSRStatus(COUNTER_BIT)
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ddmtd_counter = Signal(COUNTER_BIT)
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gtx_period_sys = Signal(COUNTER_BIT)
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gtx_tag_sys = Signal(COUNTER_BIT)
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main_tag_sys = Signal(COUNTER_BIT)
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period_colr_stb_sys = Signal()
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phase_colr_stb_sys = Signal()
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# # #
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self.helper_reset = CSRStorage(reset=1)
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self.clock_domains.cd_helper = ClockDomain()
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self.helper_reset.storage.attr.add("no_retiming")
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self.specials += [
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Instance("IBUFGDS",
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i_I=helper_dcxo_pads.p, i_IB=helper_dcxo_pads.n,
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o_O=self.cd_helper.clk),
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AsyncResetSynchronizer(self.cd_helper, self.helper_reset.storage)
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]
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self.submodules.frequency_counter = FrequencyCounter()
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self.submodules.ddmtd_sampler = DDMTDSamplerGTX(gtx, main_dcxo_pads)
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self.sync.helper += ddmtd_counter.eq(ddmtd_counter + 1)
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self.submodules.ddmtd_gtx = DDMTD(ddmtd_counter, self.ddmtd_sampler.gtx_beating)
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self.submodules.ddmtd_main = DDMTD(ddmtd_counter, self.ddmtd_sampler.main_beating)
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# DDMTD tags collection
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self.submodules.collector = ClockDomainsRenamer("helper")(Collector(COUNTER_BIT))
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self.comb += [
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self.collector.gtx_stb.eq(self.ddmtd_gtx.h_tag_update),
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self.collector.main_stb.eq(self.ddmtd_main.h_tag_update),
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self.collector.tag_gtx.eq(self.ddmtd_gtx.h_tag),
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self.collector.tag_main.eq(self.ddmtd_main.h_tag)
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]
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period_colr_stb_ps = PulseSynchronizer("helper", "sys")
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phase_colr_stb_ps = PulseSynchronizer("helper", "sys")
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self.submodules += [
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period_colr_stb_ps,
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phase_colr_stb_ps
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]
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self.sync.helper += [
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period_colr_stb_ps.i.eq(self.collector.out_period_stb),
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phase_colr_stb_ps.i.eq(self.collector.out_phase_stb)
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]
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self.sync += [
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period_colr_stb_sys.eq(period_colr_stb_ps.o),
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phase_colr_stb_sys.eq(phase_colr_stb_ps.o)
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]
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self.specials += [
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MultiReg(self.collector.out_beating_period, gtx_period_sys),
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MultiReg(self.collector.out_tag_gtx, gtx_tag_sys),
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MultiReg(self.collector.out_tag_main, main_tag_sys)
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]
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self.sync += [
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If(period_colr_stb_sys,
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self.gtx_period.status.eq(gtx_period_sys),
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),
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If(phase_colr_stb_sys,
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self.gtx_tag.status.eq(gtx_tag_sys),
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self.main_tag.status.eq(main_tag_sys)
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)
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]
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# PL-PS shared peripheral interrupt (SPI)
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self.submodules.period_ev = EventManager()
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self.period_ev.stb = EventSourcePulse()
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self.period_ev.finalize()
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self.submodules.phase_ev = EventManager()
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self.phase_ev.stb = EventSourcePulse()
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self.phase_ev.finalize()
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self.sync += [
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self.period_ev.stb.trigger.eq(period_colr_stb_sys),
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self.phase_ev.stb.trigger.eq(phase_colr_stb_sys)
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]
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