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qc2: add 4 edge counters to the end of rtio

This commit is contained in:
mwojcik 2022-11-03 10:35:45 +08:00 committed by Sebastien Bourdeauducq
parent c484153348
commit 0c1036cb0c
2 changed files with 18 additions and 1 deletions
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8
examples/device_db.py
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@ -78,6 +78,14 @@ device_db["ad9914dds1"] = {
"arguments": {"sysclk": 3e9, "bus_channel": 50, "channel": 1}, "arguments": {"sysclk": 3e9, "bus_channel": 50, "channel": 1},
} }
for i in range(4):
device_db["ttl"+str(i)+"_counter"] = {
"type": "local",
"module": "artiq.coredevice.edge_counter",
"class": "EdgeCounter",
"arguments": {"channel": 52+i}
}
# for ARTIQ test suite # for ARTIQ test suite
device_db.update( device_db.update(
loop_out="ttl0", loop_out="ttl0",

11
src/gateware/zc706.py
View File

@ -13,7 +13,7 @@ from misoc.interconnect.csr import *
from misoc.integration import cpu_interface from misoc.integration import cpu_interface
from artiq.gateware import rtio, nist_clock, nist_qc2 from artiq.gateware import rtio, nist_clock, nist_qc2
from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, dds, spi2 from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, dds, spi2, edge_counter
import dma import dma
import analyzer import analyzer
@ -215,6 +215,7 @@ class NIST_QC2(ZC706):
platform.add_extension(leds_fmc33) platform.add_extension(leds_fmc33)
rtio_channels = [] rtio_channels = []
edge_counter_phy = []
for i in range(4): for i in range(4):
phy = ttl_simple.Output(platform.request("user_led_33", i)) phy = ttl_simple.Output(platform.request("user_led_33", i))
@ -226,6 +227,9 @@ class NIST_QC2(ZC706):
phy = ttl_serdes_7series.InOut_8X(platform.request("ttl", i)) phy = ttl_serdes_7series.InOut_8X(platform.request("ttl", i))
self.submodules += phy self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512)) rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
# first four TTLs will also have edge counters
if i < 4:
edge_counter_phy.append(phy)
# CLK0, CLK1 are for clock generators, on backplane SMP connectors # CLK0, CLK1 are for clock generators, on backplane SMP connectors
for i in range(2): for i in range(2):
@ -245,6 +249,11 @@ class NIST_QC2(ZC706):
platform.request("dds", backplane_offset), 12, onehot=True) platform.request("dds", backplane_offset), 12, onehot=True)
self.submodules += phy self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4)) rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
for phy in edge_counter_phy:
counter = edge_counter.SimpleEdgeCounter(phy.input_state)
self.submodules += counter
rtio_channels.append(rtio.Channel.from_phy(counter))
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels) self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
rtio_channels.append(rtio.LogChannel()) rtio_channels.append(rtio.LogChannel())