M-Labs/artiq-zynq
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analyzer: drive wid and wstrb

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Sebastien Bourdeauducq 2020-07-15 23:11:19 +08:00
parent 8e758ecc17
commit 0b0ca8de49
1 changed files with 3 additions and 1 deletions
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src/gateware/analyzer.py
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@ -52,9 +52,11 @@ class AXIDMAWriter(Module, AutoCSR):
] ]
self.comb += [ self.comb += [
membus.w.id.eq(0),
membus.w.valid.eq(self.sink.stb), membus.w.valid.eq(self.sink.stb),
self.sink.ack.eq(membus.w.ready), self.sink.ack.eq(membus.w.ready),
membus.w.data.eq(self.sink.data) membus.w.data.eq(self.sink.data),
membus.w.strb.eq(2**(dw//8)-1),
] ]
beat_count = Signal(max=burst_length) beat_count = Signal(max=burst_length)
self.sync += [ self.sync += [