M-Labs/artiq-zynq
10
1
Fork 19
Code Issues 12 Pull Requests Releases Wiki Activity

szl: flush now write-buffered dcache of DDR pages before executing instructions in them

Browse Source
This commit is contained in:
Astro 2020-06-18 18:33:47 +02:00
parent f750234cb5
commit 06ad8dfe27
1 changed files with 7 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
src/szl/src/main.rs
View File

@ -7,6 +7,7 @@ use core::mem;
use log::{info, error}; use log::{info, error};
use cstr_core::CStr; use cstr_core::CStr;
use libcortex_a9::cache::dcci_slice;
use libboard_zynq::{ use libboard_zynq::{
self as zynq, clocks::Clocks, clocks::source::{ClockSource, ArmPll, IoPll}, self as zynq, clocks::Clocks, clocks::source::{ClockSource, ArmPll, IoPll},
logger, logger,
@ -48,6 +49,12 @@ pub fn main_core0() {
if result < 0 { if result < 0 {
error!("decompression failed"); error!("decompression failed");
} else { } else {
// Flush data cache entries for all of DDR, including
// Memory/Instruction Symchronization Barriers
dcci_slice(unsafe {
core::slice::from_raw_parts(ddr.ptr::<u8>(), ddr.size())
});
// Start core0 only, for compatibility with FSBL. // Start core0 only, for compatibility with FSBL.
info!("executing payload"); info!("executing payload");
unsafe { unsafe {