M-Labs/artiq-zynq
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restore ultrascale

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mwojcik 2021-11-29 13:03:21 +08:00
parent c43d5ba492
commit 015ec8e88f
1 changed files with 1 additions and 1 deletions
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src/gateware/zc706.py
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@ -403,7 +403,7 @@ class _SatelliteBase(SoCCore):
self.submodules.siphaser = SiPhaser7Series(
si5324_clkin=platform.request("si5324_clkin"),
rx_synchronizer=self.rx_synchronizer,
ultrascale=True,
ultrascale=False,
rtio_clk_freq=self.drtio_transceiver.rtio_clk_freq)
platform.add_false_path_constraints(
self.ps7.cd_sys.clk, self.siphaser.mmcm_freerun_output)