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artiq-zynq
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artiq-zynq/src/runtime/Cargo.toml

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add hello world firmware
2020-04-11 20:19:39 +08:00
[package]
name = "runtime"
description = "ARTIQ runtime on Zynq"
version = "0.1.0"
use consistent authors in Cargo.toml
2020-04-12 18:47:46 +08:00
authors = ["M-Labs"]
add hello world firmware
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edition = "2018"
[features]
runtime: switch to libio/libboard_artiq, add DRTIO mastering support Reviewed-on: https://git.m-labs.hk/M-Labs/artiq-zynq/pulls/137 Co-authored-by: mwojcik <mw@m-labs.hk> Co-committed-by: mwojcik <mw@m-labs.hk>
2021-10-06 13:05:45 +08:00
target_zc706 = ["libboard_zynq/target_zc706", "libsupport_zynq/target_zc706", "libconfig/target_zc706", "libboard_artiq/target_zc706"]
target_kasli_soc = ["libboard_zynq/target_kasli_soc", "libsupport_zynq/target_kasli_soc", "libconfig/target_kasli_soc", "libboard_artiq/target_kasli_soc"]
add hello world firmware
2020-04-11 20:19:39 +08:00
default = ["target_zc706"]
runtime: switch to libio/libboard_artiq, add DRTIO mastering support Reviewed-on: https://git.m-labs.hk/M-Labs/artiq-zynq/pulls/137 Co-authored-by: mwojcik <mw@m-labs.hk> Co-committed-by: mwojcik <mw@m-labs.hk>
2021-10-06 13:05:45 +08:00
[build-dependencies]
build_zynq = { path = "../libbuild_zynq" }
add hello world firmware
2020-04-11 20:19:39 +08:00
[dependencies]
add libdyld from ARTIQ e8b73876ab60e202bec0a2e5119bd7b740d0c78d
2020-04-12 18:40:15 +08:00
num-traits = { version = "0.2", default-features = false }
num-derive = "0.3"
add RTIO syscalls
2020-04-12 20:15:01 +08:00
cslice = "0.3"
runtime: init the logger
2020-04-22 07:03:58 +08:00
log = "0.4"
add RTIO PLL and clock source selection
2020-07-08 19:58:13 +08:00
nb = "0.1"
embedded-hal = "0.2"
SD reader: optimized stack and binary size
2020-06-18 11:33:18 +08:00
core_io = { version = "0.1", features = ["collections"] }
replace libio with core_io * based on https://github.com/jethrogb/rust-core_io but could not get the packaging scripts to work and the repos is unmaintained anyway, so just copied the result * more features and more up-to-date * compatible with the fatfs crate
2020-06-05 17:14:36 +08:00
byteorder = { version = "1.3", default-features = false }
moninj: sort out futures::select!
2020-04-25 20:31:38 +08:00
void = { version = "1", default-features = false }
futures = { version = "0.3", default-features = false, features = ["async-await"] }
rpc: use async-recursion
2020-06-07 21:30:33 +08:00
async-recursion = "0.3"
mgmt: Implemented network log access.
2020-07-13 15:00:53 +08:00
log_buffer = { version = "1.2" }
expose libm functions to kernel
2020-07-21 13:50:33 +08:00
libm = { version = "0.2", features = ["unstable"] }
runtime: implement acpki RTIO output
2020-08-04 17:32:43 +08:00
vcell = "0.1"
add RTIO PLL and clock source selection
2020-07-08 19:58:13 +08:00
libconfig/net_settings: made ipv6 optional feature This is to prepare for szl, which cannot use ipv6 due to memory limitation.
2020-09-01 14:34:54 +08:00
libboard_zynq = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git", features = ["ipv6"]}
update dependencies, zc706 -> zynq-rs
2020-08-06 20:33:23 +08:00
libsupport_zynq = { default-features = false, features = ["alloc_core"], git = "https://git.m-labs.hk/M-Labs/zynq-rs.git" }
libcortex_a9 = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git" }
libasync = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git" }
libregister = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git" }
use liconfig, libcoreio, szl from zynq-rs
2020-09-09 18:44:12 +08:00
libconfig = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git", features = ["ipv6"] }
add RTIO PLL and clock source selection
2020-07-08 19:58:13 +08:00
add libdyld from ARTIQ e8b73876ab60e202bec0a2e5119bd7b740d0c78d
2020-04-12 18:40:15 +08:00
dyld = { path = "../libdyld" }
Added libpanic_unwind/dwarf from rustc as libdwarf.
2020-06-30 17:22:44 +08:00
dwarf = { path = "../libdwarf" }
Libunwind: build libunwind with rust bindings
2020-06-30 17:19:09 +08:00
unwind = { path = "../libunwind" }
libc = { path = "../libc" }
runtime: switch to libio/libboard_artiq, add DRTIO mastering support Reviewed-on: https://git.m-labs.hk/M-Labs/artiq-zynq/pulls/137 Co-authored-by: mwojcik <mw@m-labs.hk> Co-committed-by: mwojcik <mw@m-labs.hk>
2021-10-06 13:05:45 +08:00
io = { path = "../libio" }
libboard_artiq = { path = "../libboard_artiq" }