320 lines
11 KiB
ArmAsm
Executable File
320 lines
11 KiB
ArmAsm
Executable File
.global _boot
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.global _start
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.global data_abort_handler
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.global _vector_table
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.global MMUTable
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.set vector_base, _vector_table
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.set TblBase, MMUTable
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.set UncachableStart, __uncachable_start
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.set UncachableEnd, __uncachable_end
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.set CRValMmuCac, 0b01000000000101 /* Enable IDC, and MMU */
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.set PSS_SLCR_BASE_ADDR, 0xF8000000
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.set PSS_L2CC_BASE_ADDR, 0xF8F02000
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.set L2CCWay, (PSS_L2CC_BASE_ADDR + 0x077C) /*(PSS_L2CC_BASE_ADDR + PSS_L2CC_CACHE_INVLD_WAY_OFFSET)*/
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.set L2CCSync, (PSS_L2CC_BASE_ADDR + 0x0730) /*(PSS_L2CC_BASE_ADDR + PSS_L2CC_CACHE_SYNC_OFFSET)*/
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.set L2CCCrtl, (PSS_L2CC_BASE_ADDR + 0x0100) /*(PSS_L2CC_BASE_ADDR + PSS_L2CC_CNTRL_OFFSET)*/
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.set L2CCAuxCrtl, (PSS_L2CC_BASE_ADDR + 0x0104) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_AUX_CNTRL_OFFSET)*/
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.set L2CCTAGLatReg, (PSS_L2CC_BASE_ADDR + 0x0108) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_TAG_RAM_CNTRL_OFFSET)*/
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.set L2CCDataLatReg, (PSS_L2CC_BASE_ADDR + 0x010C) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_DATA_RAM_CNTRL_OFFSET)*/
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.set L2CCIntClear, (PSS_L2CC_BASE_ADDR + 0x0220) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_IAR_OFFSET)*/
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.set L2CCIntRaw, (PSS_L2CC_BASE_ADDR + 0x021C) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_ISR_OFFSET)*/
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.set L2CCAuxControl, 0x72360000 /* Enable all prefetching, Cache replacement policy, Parity enable,
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Event monitor bus enable and Way Size (64 KB) */
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.set L2CCControl, 0x01 /* Enable L2CC */
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.set L2CCTAGLatency, 0x0111 /* latency for TAG RAM */
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.set L2CCDataLatency, 0x0121 /* latency for DATA RAM */
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.set SLCRlockReg, (PSS_SLCR_BASE_ADDR + 0x04) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_LOCK_OFFSET)*/
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.set SLCRUnlockReg, (PSS_SLCR_BASE_ADDR + 0x08) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_UNLOCK_OFFSET)*/
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.set SLCRL2cRamReg, (PSS_SLCR_BASE_ADDR + 0xA1C) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_L2C_RAM_OFFSET)*/
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.set SLCRlockKey, 0x767B /* SLCR lock key */
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.set SLCRUnlockKey, 0xDF0D /* SLCR unlock key */
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.set SLCRL2cRamConfig, 0x00020202 /* SLCR L2C ram configuration */
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.org 0
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.text
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.globl _vector_table
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.section .vectors
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_vector_table:
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B _boot
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B Undefined
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B SVCHandler
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B PrefetchAbortHandler
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B DataAbortHandler
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NOP /* Placeholder for address exception vector*/
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B IRQHandler
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B FIQHandler
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.text
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_boot:
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// Read MPIDR to determine processor id
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mrc p15,0,r0,c0,c0,5
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and r0, r0, 0x3
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cmp r0, 0
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// processor 0 -> p0_boot
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// processor 1 waits for interrupt, then goes via p1_boot
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beq p0_start
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ldr r13,.Lstack2 /* stack address */
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p1_loop:
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wfi
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b p1_loop
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p0_start:
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/* set VBAR to the _vector_table address in linker script */
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ldr r0, =vector_base
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mcr p15, 0, r0, c12, c0, 0
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/*invalidate scu*/
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ldr r7, =0xf8f0000c
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ldr r6, =0xffff
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str r6, [r7]
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/* Invalidate caches and TLBs */
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mov r0,#0 /* r0 = 0 */
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mcr p15, 0, r0, c8, c7, 0 /* invalidate TLBs */
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mcr p15, 0, r0, c7, c5, 0 /* invalidate icache */
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mcr p15, 0, r0, c7, c5, 6 /* Invalidate branch predictor array */
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bl invalidate_dcache /* invalidate dcache */
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/* Disable MMU, if enabled */
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mrc p15, 0, r0, c1, c0, 0 /* read CP15 register 1 */
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bic r0, r0, #0x1 /* clear bit 0 */
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mcr p15, 0, r0, c1, c0, 0 /* write value back */
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/* Mark the a section of DDR as uncacheable */
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ldr r3, =UncachableStart
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ldr r4, =UncachableEnd
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ldr r0, =TblBase /* MMU Table address in memory */
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ldr r2, =0x11de2 /* S=b1 TEX=b001 AP=b11, Domain=b1111, C=b0, B=b0 */
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lsr r5, r3, #18 // Calculate table offset
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add r0, r0, r5 // Address of first table entry to modify
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uncacheable_loop:
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add r5, r3, r2
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str r5, [r0] // write the entry to MMU table
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add r0, r0, #0x4 // next entry in the table
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add r3, r3, #0x100000 // next section
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cmp r3, r4
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blt uncacheable_loop
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/*set scu enable bit in scu*/
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ldr r7, =0xf8f00000
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ldr r0, [r7]
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orr r0, r0, #0x1
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str r0, [r7]
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// enable MMU and cache
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ldr r0,=TblBase /* Load MMU translation table base */
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orr r0, r0, #0x5B /* Outer-cacheable, WB */
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mcr p15, 0, r0, c2, c0, 0 /* TTB0 */
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mvn r0,#0 /* Load MMU domains -- all ones=manager */
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mcr p15,0,r0,c3,c0,0
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// Enable mmu, icache and dcache
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ldr r0,=CRValMmuCac
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mcr p15,0,r0,c1,c0,0 /* Enable cache and MMU */
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dsb /* dsb allow the MMU to start up */
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isb /* isb flush prefetch buffer */
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/* Write to ACTLR */
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mrc p15, 0, r0, c1, c0, 1 /* Read ACTLR*/
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orr r0, r0, #(0x01 << 6) /* set SMP bit */
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orr r0, r0, #(0x01 ) /* Cache/TLB maintenance broadcast */
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mcr p15, 0, r0, c1, c0, 1 /* Write ACTLR*/
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/* Invalidate L2 Cache and enable L2 Cache*/
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ldr r0,=L2CCCrtl /* Load L2CC base address base + control register */
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mov r1, #0 /* force the disable bit */
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str r1, [r0] /* disable the L2 Caches */
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ldr r0,=L2CCAuxCrtl /* Load L2CC base address base + Aux control register */
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ldr r1,[r0] /* read the register */
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ldr r2,=L2CCAuxControl /* set the default bits */
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orr r1,r1,r2
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str r1, [r0] /* store the Aux Control Register */
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ldr r0,=L2CCTAGLatReg /* Load L2CC base address base + TAG Latency address */
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ldr r1,=L2CCTAGLatency /* set the latencies for the TAG*/
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str r1, [r0] /* store the TAG Latency register Register */
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ldr r0,=L2CCDataLatReg /* Load L2CC base address base + Data Latency address */
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ldr r1,=L2CCDataLatency /* set the latencies for the Data*/
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str r1, [r0] /* store the Data Latency register Register */
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ldr r0,=L2CCWay /* Load L2CC base address base + way register*/
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ldr r2, =0xFFFF
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str r2, [r0] /* force invalidate */
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ldr r0,=L2CCSync /* need to poll 0x730, PSS_L2CC_CACHE_SYNC_OFFSET */
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/* Load L2CC base address base + sync register*/
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/* poll for completion */
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Sync: ldr r1, [r0]
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cmp r1, #0
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bne Sync
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ldr r0,=L2CCIntRaw /* clear pending interrupts */
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ldr r1,[r0]
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ldr r0,=L2CCIntClear
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str r1,[r0]
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ldr r0,=SLCRUnlockReg /* Load SLCR base address base + unlock register */
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ldr r1,=SLCRUnlockKey /* set unlock key */
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str r1, [r0] /* Unlock SLCR */
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ldr r0,=SLCRL2cRamReg /* Load SLCR base address base + l2c Ram Control register */
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ldr r1,=SLCRL2cRamConfig /* set the configuration value */
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str r1, [r0] /* store the L2c Ram Control Register */
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ldr r0,=SLCRlockReg /* Load SLCR base address base + lock register */
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ldr r1,=SLCRlockKey /* set lock key */
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str r1, [r0] /* lock SLCR */
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ldr r0,=L2CCCrtl /* Load L2CC base address base + control register */
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ldr r1,[r0] /* read the register */
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mov r2, #L2CCControl /* set the enable bit */
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orr r1,r1,r2
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str r1, [r0] /* enable the L2 Caches */
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mov r0,r0
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// Enable CP11 and CP10 access from all processor modes
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mrc p15, 0, r0, c1, c0, 2 // Read CPACR
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orr r0, r0, (0b1111<<20)
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mcr p15, 0, r0, c1, c0, 2
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/* enable vfp */
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vmrs r1, fpexc
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orr r1,r1, (1<<30)
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vmsr fpexc, r1
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mrc p15,0,r0,c1,c0,0 /* flow prediction enable */
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orr r0, r0, #(0x01 << 11) /* #0x8000 */
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mcr p15,0,r0,c1,c0,0
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mrc p15,0,r0,c1,c0,1 /* read Auxiliary Control Register */
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orr r0, r0, #(0x1 << 2) /* enable Dside prefetch */
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orr r0, r0, #(0x1 << 1) /* enable L2 Prefetch hint */
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mcr p15,0,r0,c1,c0,1 /* write Auxiliary Control Register */
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mrs r0, cpsr /* get the current PSR */
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bic r0, r0, #0x100 /* enable asynchronous abort exception */
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msr cpsr_xsf, r0
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// Enable and reset cycle counter
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mov r0, 0b101
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mcr p15, 0, r0, c9, c12, 0
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.Lenclsbss:
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/* clear bss */
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ldr r1,.Lbss_start /* calculate beginning of the BSS */
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ldr r2,.Lbss_end /* calculate end of the BSS */
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.Lloop_bss:
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cmp r1,r2
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bge .Lenclbss /* If no BSS, no clearing required */
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str r0, [r1], #4
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b .Lloop_bss
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.Lenclbss:
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/* set stack pointer */
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ldr r13,.Lstack /* stack address */
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bl main
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loop:
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b loop
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Undefined:
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ldr r13, .Lstack
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mov r0, lr // address of undefined instruction +8
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b undefined_instruction_handler
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SVCHandler:
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b SVCHandler
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PrefetchAbortHandler:
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b PrefetchAbortHandler
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DataAbortHandler:
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ldr r13, .Lstack
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mov r0, lr // address of aborted instruction +8
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mrc p15, 0, r1, c6, c0, 0 // Read DFAR
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mrc p15, 0, r2, c5, c0, 0 // Read DFSR
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b data_abort_handler
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IRQHandler:
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ldr r13, .Lstack
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b irq_handler
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FIQHandler:
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b FIQHandler
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invalidate_dcache:
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mrc p15, 1, r0, c0, c0, 1 /* read CLIDR */
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ands r3, r0, #0x7000000
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mov r3, r3, lsr #23 /* cache level value (naturally aligned) */
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beq finished
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mov r10, #0 /* start with level 0 */
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loop1:
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add r2, r10, r10, lsr #1 /* work out 3xcachelevel */
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mov r1, r0, lsr r2 /* bottom 3 bits are the Cache type for this level */
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and r1, r1, #7 /* get those 3 bits alone */
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cmp r1, #2
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blt skip /* no cache or only instruction cache at this level */
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mcr p15, 2, r10, c0, c0, 0 /* write the Cache Size selection register */
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isb /* isb to sync the change to the CacheSizeID reg */
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mrc p15, 1, r1, c0, c0, 0 /* reads current Cache Size ID register */
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and r2, r1, #7 /* extract the line length field */
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add r2, r2, #4 /* add 4 for the line length offset (log2 16 bytes) */
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ldr r4, =0x3ff
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ands r4, r4, r1, lsr #3 /* r4 is the max number on the way size (right aligned) */
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clz r5, r4 /* r5 is the bit position of the way size increment */
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ldr r7, =0x7fff
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ands r7, r7, r1, lsr #13 /* r7 is the max number of the index size (right aligned) */
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loop2:
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mov r9, r4 /* r9 working copy of the max way size (right aligned) */
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loop3:
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orr r11, r10, r9, lsl r5 /* factor in the way number and cache number into r11 */
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orr r11, r11, r7, lsl r2 /* factor in the index number */
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mcr p15, 0, r11, c7, c6, 2 /* invalidate by set/way */
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subs r9, r9, #1 /* decrement the way number */
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bge loop3
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subs r7, r7, #1 /* decrement the index */
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bge loop2
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skip:
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add r10, r10, #2 /* increment the cache number */
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cmp r3, r10
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bgt loop1
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finished:
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mov r10, #0 /* swith back to cache level 0 */
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mcr p15, 2, r10, c0, c0, 0 /* select current cache level in cssr */
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dsb
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isb
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bx lr
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.Lbss_start:
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.long _fbss
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.Lbss_end:
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.long _ebss
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.Lstack:
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.long _fstack
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.Lstack2:
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.long _fstack2
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