57 lines
1.7 KiB
Rust
Executable File
57 lines
1.7 KiB
Rust
Executable File
#![no_std]
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#![feature(asm)]
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include!(concat!(env!("BUILDINC_DIRECTORY"), "/generated/csr.rs"));
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pub mod uart;
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#[macro_use]
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pub mod uart_console;
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// Clean = expunge cache line with writeback
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pub fn clean_data_cache(base: usize, len: usize) {
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const CACHE_SYNC_OFFSET: isize = 0x0730/4; // Cache Sync
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const CACHE_CLEAN_PA_OFFSET: isize = 0x7B0/4;
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const L2CC_BASE: *mut u32 = 0xF8F02000 as *mut u32;
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const CACHE_LINE_LENGTH: usize = 32;
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let mut addr = base & !(CACHE_LINE_LENGTH-1);
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loop {
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if addr > base+len {break}
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unsafe {
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write_volatile(L2CC_BASE.offset(CACHE_CLEAN_PA_OFFSET), addr as u32);
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write_volatile(L2CC_BASE.offset(CACHE_SYNC_OFFSET), 0);
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// Clean data cache line by virtual address
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asm!("mcr p15, 0, $0, c7, c10, 1"::"r"(addr))
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}
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addr += CACHE_LINE_LENGTH;
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}
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}
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use core::ptr::write_volatile;
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// Invalidate = expunge cache line without writeback
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pub fn invalidate_data_cache(base: usize, len: usize) {
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const CACHE_SYNC_OFFSET: isize = 0x0730/4; // Cache Sync
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const CACHE_INVLD_PA_OFFSET: isize = 0x0770/4; // Cache Invalid by PA
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const L2CC_BASE: *mut u32 = 0xF8F02000 as *mut u32;
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const CACHE_LINE_LENGTH: usize = 32;
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let mut addr = base & !(CACHE_LINE_LENGTH-1);
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loop {
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if addr > base+len {break}
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unsafe {
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write_volatile(L2CC_BASE.offset(CACHE_INVLD_PA_OFFSET), addr as u32);
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write_volatile(L2CC_BASE.offset(CACHE_SYNC_OFFSET), 0);
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// Invalidate data cache line by virtual address
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asm!("mcr p15, 0, $0, c7, c6, 1"::"r"(addr))
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}
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addr += CACHE_LINE_LENGTH;
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}
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}
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