178 wiersze
6.0 KiB
Python
Executable File
178 wiersze
6.0 KiB
Python
Executable File
#!/usr/bin/env python
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from migen_axi.integration.soc_core import SoCCore
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from migen_axi.platforms import zedboard
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from migen import *
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from misoc.interconnect.csr import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.genlib.cdc import MultiReg
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from misoc.integration.builder import *
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from artiq.gateware import rtio
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from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, spi2
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from artiq.gateware.rtio.phy import ttl_serdes_7series, ttl_simple
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from maxi_dma import MAXI_DMA, DMA_KernelInitiator, DMA_Test
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from hp_dma import HP_DMA_READ
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from operator import attrgetter
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import argparse
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import os
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class _RTIOCRG(Module, AutoCSR):
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def __init__(self):
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self._pll_reset = CSRStorage(reset=1)
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self._pll_locked = CSRStatus()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_rtio = ClockDomain()
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# self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)
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pll_locked = Signal()
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rtio_clk = Signal()
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rtiox4_clk = Signal()
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self.specials += [
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Instance("PLLE2_ADV",
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p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
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p_REF_JITTER1=0.24,
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p_CLKIN1_PERIOD=8.0, p_CLKIN2_PERIOD=8.0,
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i_CLKIN2=self.cd_sys.clk,
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# Warning: CLKINSEL=0 means CLKIN2 is selected
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i_CLKINSEL=0,
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# VCO @ 1GHz when using 125MHz input
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p_CLKFBOUT_MULT=8, p_DIVCLK_DIVIDE=1,
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i_CLKFBIN=self.cd_rtio.clk,
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i_RST=self._pll_reset.storage,
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o_CLKFBOUT=rtio_clk,
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# p_CLKOUT0_DIVIDE=2, p_CLKOUT0_PHASE=0.0,
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# o_CLKOUT0=rtiox4_clk
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),
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Instance("BUFG", i_I=rtio_clk, o_O=self.cd_rtio.clk),
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# Instance("BUFG", i_I=rtiox4_clk, o_O=self.cd_rtiox4.clk),
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AsyncResetSynchronizer(self.cd_rtio, ~pll_locked),
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MultiReg(pll_locked, self._pll_locked.status)
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]
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def fix_serdes_timing_path(platform):
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# ignore timing of path from OSERDESE2 through the pad to ISERDESE2
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platform.add_platform_command(
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"set_false_path -quiet "
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"-through [get_pins -filter {{REF_PIN_NAME == OQ || REF_PIN_NAME == TQ}} "
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"-of [get_cells -filter {{REF_NAME == OSERDESE2}}]] "
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"-to [get_pins -filter {{REF_PIN_NAME == D}} "
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"-of [get_cells -filter {{REF_NAME == ISERDESE2}}]]"
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)
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class Zedboard(SoCCore):
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def __init__(self):
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plat = zedboard.Platform()
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super().__init__(platform=plat)
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fclk0 = self.ps7.fclk.clk[0]
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self.clock_domains.cd_sys = ClockDomain()
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self.specials += Instance("BUFG", i_I=fclk0, o_O=self.cd_sys.clk),
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plat.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
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plat.add_platform_command("set_input_jitter clk_fpga_0 0.24")
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self.evento_stb = Signal()
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evento_latched = Signal()
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evento_latched_d = Signal()
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self.sync += evento_latched.eq(self.ps7.event.o)
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self.sync += evento_latched_d.eq(evento_latched)
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self.comb += self.evento_stb.eq(evento_latched != evento_latched_d)
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self.submodules.hp_dma = HP_DMA_READ(bus=self.ps7.s_axi_hp0)
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self.csr_devices.append("hp_dma")
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# Debug ports
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# pads_b = plat.request("pmod",1)
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# ar, aw, w, r, b = attrgetter("ar", "aw", "w", "r", "b")(self.dma.bus)
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# self.comb += pads_b[0].eq(self.dma.trigger_stb)
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self.rtio_channels = []
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for i in range(4):
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pad = plat.request("user_led", i)
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phy = ttl_simple.InOut(pad)
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self.submodules += phy
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self.rtio_channels.append(rtio.Channel.from_phy(phy))
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for i in range(4):
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led = plat.request("user_led", i+4)
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s = Signal()
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btn = plat.request("user_btn", i)
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self.comb += led.eq(s | btn)
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self.comb += s.eq(self.ps7.gpio.o[i])
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pads = plat.request("pmod",0)
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for i in range(8):
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phy = ttl_simple.InOut(pads[i])
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self.submodules += phy
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self.rtio_channels.append(rtio.Channel.from_phy(phy))
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self.add_rtio(self.rtio_channels)
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def add_rtio(self, rtio_channels):
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self.submodules.rtio_crg = _RTIOCRG()
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self.csr_devices.append("rtio_crg")
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self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
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self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels)
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self.csr_devices.append("rtio_core")
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self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc)
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self.csr_devices.append("rtio")
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self.submodules.dma = MAXI_DMA(bus=self.ps7.s_axi_acp,
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user=self.ps7.s_axi_acp_user,
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trigger_stb=self.evento_stb)
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self.csr_devices.append("dma")
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self.submodules.rtio_dma = DMA_KernelInitiator(engine=self.dma)
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self.submodules.cri_con = rtio.CRIInterconnectShared(
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[self.rtio.cri, self.rtio_dma.cri],
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[self.rtio_core.cri])
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self.csr_devices.append("cri_con")
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self.platform.add_false_path_constraints(
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self.rtio_crg.cd_rtio.clk)
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self.comb += self.rtio_crg.cd_sys.clk.eq(self.cd_sys.clk)
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def main():
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parser = argparse.ArgumentParser()
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builder_args(parser)
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args = parser.parse_args()
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soc = Zedboard()
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# TODO:
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# builder = Builder(soc, **builder_argdict(args))
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# builder.software_packages = []
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# root_path = os.path.dirname(os.path.abspath(__file__))
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# builder.add_software_package("libm")
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# builder.add_software_package("libprintf")
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# builder.add_software_package("libunwind")
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# builder.add_software_package("libbase")
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# builder.add_software_package("runtime", os.path.join(root_path, "firmware/runtime"))
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# builder.build()
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soc.build()
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if __name__ == "__main__":
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main()
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