186 lines
7.6 KiB
ArmAsm
186 lines
7.6 KiB
ArmAsm
/*****************************************************************************/
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/**
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* @file translation_table.s
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*
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* @addtogroup a9_boot_code
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* @{
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* <h2> translation_table.S </h2>
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* translation_table.S contains a static page table required by MMU for
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* cortex-A9. This translation table is flat mapped (input address = output
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* address) with default memory attributes defined for zynq architecture. It
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* utilizes short descriptor translation table format with each section defining
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* 1MB of memory.
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*
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* The overview of translation table memory attributes is described below.
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*
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*| | Memory Range | Definition in Translation Table |
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*|-----------------------|-------------------------|-----------------------------------|
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*| DDR | 0x00000000 - 0x3FFFFFFF | Normal write-back Cacheable |
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*| PL | 0x40000000 - 0xBFFFFFFF | Strongly Ordered |
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*| Reserved | 0xC0000000 - 0xDFFFFFFF | Unassigned |
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*| Memory mapped devices | 0xE0000000 - 0xE02FFFFF | Device Memory |
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*| Reserved | 0xE0300000 - 0xE0FFFFFF | Unassigned |
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*| NAND, NOR | 0xE1000000 - 0xE3FFFFFF | Device memory |
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*| SRAM | 0xE4000000 - 0xE5FFFFFF | Normal write-back Cacheable |
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*| Reserved | 0xE6000000 - 0xF7FFFFFF | Unassigned |
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*| AMBA APB Peripherals | 0xF8000000 - 0xF8FFFFFF | Device Memory |
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*| Reserved | 0xF9000000 - 0xFBFFFFFF | Unassigned |
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*| Linear QSPI - XIP | 0xFC000000 - 0xFDFFFFFF | Normal write-through cacheable |
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*| Reserved | 0xFE000000 - 0xFFEFFFFF | Unassigned |
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*| OCM | 0xFFF00000 - 0xFFFFFFFF | Normal inner write-back cacheable |
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*
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* @note
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*
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* For region 0x00000000 - 0x3FFFFFFF, a system where DDR is less than 1GB,
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* region after DDR and before PL is marked as undefined/reserved in translation
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* table. In 0xF8000000 - 0xF8FFFFFF, 0xF8000C00 - 0xF8000FFF, 0xF8010000 -
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* 0xF88FFFFF and 0xF8F03000 to 0xF8FFFFFF are reserved but due to granual size
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* of 1MB, it is not possible to define separate regions for them. For region
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* 0xFFF00000 - 0xFFFFFFFF, 0xFFF00000 to 0xFFFB0000 is reserved but due to 1MB
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* granual size, it is not possible to define separate region for it
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- ---------------------------------------------------
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* 1.00a ecm 10/20/09 Initial version
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* 3.04a sdm 01/13/12 Updated MMU table to mark DDR memory as Shareable
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* 3.07a sgd 07/05/2012 Configuring device address spaces as shareable device
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* instead of strongly-ordered.
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* 3.07a asa 07/17/2012 Changed the property of the ".mmu_tbl" section.
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* 4.2 pkp 09/02/2014 added entries for 0xfe000000 to 0xffefffff as reserved
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* and 0xe0000000 - 0xe1ffffff is broken down into
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* 0xe0000000 - 0xe02fffff (memory mapped devides)
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* 0xe0300000 - 0xe0ffffff (reserved) and
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* 0xe1000000 - 0xe1ffffff (NAND)
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* 5.2 pkp 06/08/2015 put a check for XPAR_PS7_DDR_0_S_AXI_BASEADDR to confirm
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* if DDR is present or not and accordingly generate the
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* translation table
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* 6.1 pkp 07/11/2016 Corrected comments for memory attributes
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* </pre>
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*
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*
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******************************************************************************/
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.globl MMUTable
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.section .mmu_tbl,"a"
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MMUTable:
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/* Each table entry occupies one 32-bit word and there are
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* 4096 entries, so the entire table takes up 16KB.
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* Each entry covers a 1MB section.
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*/
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.set SECT, 0
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.set DDR_START, 0x00100000
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.set DDR_END, 0x1FFFFFFF
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.set DDR_SIZE, (DDR_END - DDR_START)+1
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.set DDR_REG, DDR_SIZE/0x100000
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.set UNDEF_REG, 0x3FF - DDR_REG
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/*0x00000000 - 0x00100000 (cacheable )*/
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.word SECT + 0x15de6 /* S=b1 TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1 */
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.set SECT, SECT+0x100000
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.rept DDR_REG /* (DDR Cacheable) */
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.word SECT + 0x15de6 /* S=b1 TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1 */
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.set SECT, SECT+0x100000
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.endr
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.rept UNDEF_REG /* (unassigned/reserved).
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* Generates a translation fault if accessed */
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.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
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.set SECT, SECT+0x100000
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.endr
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.rept 0x0400 /* 0x40000000 - 0x7fffffff (FPGA slave0) */
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.word SECT + 0xc02 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b0 */
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.set SECT, SECT+0x100000
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.endr
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.rept 0x0400 /* 0x80000000 - 0xbfffffff (FPGA slave1) */
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.word SECT + 0xc02 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b0 */
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.set SECT, SECT+0x100000
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.endr
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.rept 0x0200 /* 0xc0000000 - 0xdfffffff (unassigned/reserved).
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* Generates a translation fault if accessed */
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.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
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.set SECT, SECT+0x100000
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.endr
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.rept 0x003 /* 0xe0000000 - 0xe02fffff (Memory mapped devices)
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* UART/USB/IIC/SPI/CAN/GEM/GPIO/QSPI/SD/NAND */
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.word SECT + 0xc06 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */
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.set SECT, SECT+0x100000
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.endr
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.rept 0x0D /* 0xe0300000 - 0xe0ffffff (unassigned/reserved).
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* Generates a translation fault if accessed */
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.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
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.set SECT, SECT+0x100000
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.endr
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.rept 0x0010 /* 0xe1000000 - 0xe1ffffff (NAND) */
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.word SECT + 0xc06 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */
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.set SECT, SECT+0x100000
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.endr
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.rept 0x0020 /* 0xe2000000 - 0xe3ffffff (NOR) */
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.word SECT + 0xc06 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */
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.set SECT, SECT+0x100000
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.endr
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.rept 0x0020 /* 0xe4000000 - 0xe5ffffff (SRAM) */
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.word SECT + 0xc0e /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b1, B=b1 */
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.set SECT, SECT+0x100000
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.endr
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.rept 0x0120 /* 0xe6000000 - 0xf7ffffff (unassigned/reserved).
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* Generates a translation fault if accessed */
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.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
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.set SECT, SECT+0x100000
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.endr
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/* 0xf8000c00 to 0xf8000fff, 0xf8010000 to 0xf88fffff and
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0xf8f03000 to 0xf8ffffff are reserved but due to granual size of
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1MB, it is not possible to define separate regions for them */
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.rept 0x0010 /* 0xf8000000 - 0xf8ffffff (AMBA APB Peripherals) */
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.word SECT + 0xc06 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */
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.set SECT, SECT+0x100000
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.endr
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.rept 0x0030 /* 0xf9000000 - 0xfbffffff (unassigned/reserved).
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* Generates a translation fault if accessed */
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.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
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.set SECT, SECT+0x100000
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.endr
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.rept 0x0020 /* 0xfc000000 - 0xfdffffff (Linear QSPI - XIP) */
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.word SECT + 0xc0a /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b1, B=b0 */
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.set SECT, SECT+0x100000
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.endr
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.rept 0x001F /* 0xfe000000 - 0xffefffff (unassigned/reserved).
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* Generates a translation fault if accessed */
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.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
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.set SECT, SECT+0x100000
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.endr
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/* 0xfff00000 to 0xfffb0000 is reserved but due to granual size of
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1MB, it is not possible to define separate region for it
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0xfff00000 - 0xffffffff
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256K OCM when mapped to high address space
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inner-cacheable */
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.word SECT + 0x4c0e /* S=b0 TEX=b100 AP=b11, Domain=b0, C=b1, B=b1 */
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.set SECT, SECT+0x100000
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.end
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