From e139aa0ae9a98d232cff7433b8b0f73ac69e262b Mon Sep 17 00:00:00 2001 From: cjb Date: Thu, 4 Oct 2018 22:19:23 +0100 Subject: [PATCH] initial commit --- .gitignore | 10 + experiments/dds_timing.py | 70 + experiments/device_db.py | 147 ++ experiments/mandelbrot.py | 46 + experiments/minimal.py | 14 + experiments/ttl.py | 93 + experiments/wall_time.py | 18 + firmware/Cargo.toml | 7 + firmware/libboard_misoc/Cargo.toml | 14 + firmware/libboard_misoc/lib.rs | 56 + firmware/libboard_misoc/uart.rs | 14 + firmware/libboard_misoc/uart_console.rs | 30 + firmware/libdyld/Cargo.toml | 8 + firmware/libdyld/elf.rs | 2737 +++++++++++++++++++++++ firmware/libdyld/lib.rs | 339 +++ firmware/libksupport/._eh.rs | Bin 0 -> 4096 bytes firmware/libksupport/Cargo.toml | 20 + firmware/libksupport/api.rs | 89 + firmware/libksupport/build.rs | 12 + firmware/libksupport/eh.rs | 602 +++++ firmware/libksupport/glue.c | 68 + firmware/libksupport/lib.rs | 59 + firmware/libksupport/rtio.rs | 337 +++ firmware/libunwind-rs/Cargo.toml | 15 + firmware/libunwind-rs/build.rs | 41 + firmware/libunwind-rs/lib.rs | 29 + firmware/libunwind-rs/libunwind.rs | 273 +++ firmware/runtime/Cargo.toml | 20 + firmware/runtime/Makefile | 27 + firmware/runtime/build.rs | 17 + firmware/runtime/glue.c | 68 + firmware/runtime/lscript.ld | 83 + firmware/runtime/main.rs | 92 + firmware/runtime/startup.S | 320 +++ firmware/runtime/translation_table.S | 185 ++ hp_dma.py | 106 + load.py | 90 + maxi_dma.py | 284 +++ ps7_init.tcl | 771 +++++++ run.py | 24 + test_hp_dma.py | 46 + test_maxi_dma.py | 68 + test_rtio_dma.py | 79 + xilinx-tcl.cfg | 61 + zedboard.py | 180 ++ zynq-7000.cfg | 211 ++ 46 files changed, 7880 insertions(+) create mode 100644 .gitignore create mode 100755 experiments/dds_timing.py create mode 100755 experiments/device_db.py create mode 100755 experiments/mandelbrot.py create mode 100755 experiments/minimal.py create mode 100755 experiments/ttl.py create mode 100755 experiments/wall_time.py create mode 100755 firmware/Cargo.toml create mode 100755 firmware/libboard_misoc/Cargo.toml create mode 100755 firmware/libboard_misoc/lib.rs create mode 100755 firmware/libboard_misoc/uart.rs create mode 100755 firmware/libboard_misoc/uart_console.rs create mode 100644 firmware/libdyld/Cargo.toml create mode 100644 firmware/libdyld/elf.rs create mode 100644 firmware/libdyld/lib.rs create mode 100644 firmware/libksupport/._eh.rs create mode 100755 firmware/libksupport/Cargo.toml create mode 100755 firmware/libksupport/api.rs create mode 100755 firmware/libksupport/build.rs create mode 100644 firmware/libksupport/eh.rs create mode 100755 firmware/libksupport/glue.c create mode 100755 firmware/libksupport/lib.rs create mode 100755 firmware/libksupport/rtio.rs create mode 100755 firmware/libunwind-rs/Cargo.toml create mode 100755 firmware/libunwind-rs/build.rs create mode 100755 firmware/libunwind-rs/lib.rs create mode 100755 firmware/libunwind-rs/libunwind.rs create mode 100755 firmware/runtime/Cargo.toml create mode 100755 firmware/runtime/Makefile create mode 100755 firmware/runtime/build.rs create mode 100755 firmware/runtime/glue.c create mode 100755 firmware/runtime/lscript.ld create mode 100755 firmware/runtime/main.rs create mode 100755 firmware/runtime/startup.S create mode 100755 firmware/runtime/translation_table.S create mode 100755 hp_dma.py create mode 100755 load.py create mode 100755 maxi_dma.py create mode 100755 ps7_init.tcl create mode 100755 run.py create mode 100755 test_hp_dma.py create mode 100755 test_maxi_dma.py create mode 100755 test_rtio_dma.py create mode 100755 xilinx-tcl.cfg create mode 100755 zedboard.py create mode 100644 zynq-7000.cfg diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..98d8499 --- /dev/null +++ b/.gitignore @@ -0,0 +1,10 @@ +gateware/build +misoc_* +*.o +*.a +*.d +*.elf +*.bin +*.lock +*.vcd +__pycache__ diff --git a/experiments/dds_timing.py b/experiments/dds_timing.py new file mode 100755 index 0000000..5338d41 --- /dev/null +++ b/experiments/dds_timing.py @@ -0,0 +1,70 @@ +from artiq.experiment import * +import numpy as np + +class Benchmark(EnvExperiment): + def build(self): + self.setattr_device("core") + self.dds = self.get_device("urukul0_ch0") + + @kernel + def bisect_underflow(self, f, t_max_mu=1000, t_min_mu=0): + t = 0 + while (t_max_mu-t_min_mu) > 2: + t = np.int64( (t_max_mu+t_min_mu)/2 ) + print(np.int32(t_min_mu), np.int32(t_max_mu)) + try: + f(t) + except RTIOUnderflow: + print("Underflow") + if t == t_max_mu: + raise ValueError("Upper bound underflowed") + t_min_mu = t + else: + t_max_mu = t + return t + + @kernel + def dds_update_rate(self): + t=0 + def f(t): + self.core.reset() + for i in range(1000): + with parallel: + delay_mu(t) + self.dds.set(80*MHz, amplitude=0.1, phase=0.5) + t = self.bisect_underflow(lambda t: f(t), t_max_mu=50000) + print("Sustained DDS update time: ", np.int32(t), "mu") + + @kernel + def dds_setmu_update_rate(self): + t=0 + + def f(t): + f_mu = self.dds.frequency_to_ftw(80*MHz) + amp_mu = self.dds.amplitude_to_asf(0.1) + phase_mu = self.dds.turns_to_pow(0.5) + self.core.reset() + for i in range(1000): + with parallel: + delay_mu(t) + self.dds.set_mu(f_mu, asf=amp_mu, pow=phase_mu) + t = self.bisect_underflow(lambda t: f(t), t_max_mu=50000) + print("Sustained DDS set_mu update time: ", np.int32(t), "mu") + + @kernel + def measure_dds_timeline_advance(self): + self.core.break_realtime() + t0 = now_mu() + self.dds.set(80*MHz, amplitude=0.1, phase=0.5) + dt = now_mu()-t0 + core_log("DDS timeline advance:", np.int32(dt), "mu") + + @kernel + def run(self): + self.core.reset() + self.dds.cpld.init(blind=True) + self.dds.init(blind=True) + + # self.measure_dds_timeline_advance() + self.dds_update_rate() + # self.dds_setmu_update_rate() diff --git a/experiments/device_db.py b/experiments/device_db.py new file mode 100755 index 0000000..84f6d9e --- /dev/null +++ b/experiments/device_db.py @@ -0,0 +1,147 @@ +device_db = { + "core": { + "type": "local", + "module": "artiq.coredevice.core", + "class": "Core", + "arguments": {"host": "lalala", "ref_period": 1/(125e6), "ref_multiplier": 1} + }, + + "ttl0": { + "type": "local", + "module": "artiq.coredevice.ttl", + "class": "TTLInOut", + "arguments": {"channel": 0}, + }, + + + + "spi_urukul0": { + "type": "local", + "module": "artiq.coredevice.spi2", + "class": "SPIMaster", + "arguments": {"channel": 12} + }, + "ttl_urukul0_io_update": { + "type": "local", + "module": "artiq.coredevice.ttl", + "class": "TTLOut", + "arguments": {"channel": 13} + }, + "urukul0_cpld": { + "type": "local", + "module": "artiq.coredevice.urukul", + "class": "CPLD", + "arguments": { + "spi_device": "spi_urukul0", + "io_update_device": "ttl_urukul0_io_update", + "refclk": 125e6, + "clk_sel": 1 + } + }, + "urukul0_ch0": { + "type": "local", + "module": "artiq.coredevice.ad9910", + "class": "AD9910", + "arguments": { + "pll_n": 32, + "chip_select": 4, + "cpld_device": "urukul0_cpld", + } + }, + "urukul0_ch1": { + "type": "local", + "module": "artiq.coredevice.ad9910", + "class": "AD9910", + "arguments": { + "pll_n": 32, + "chip_select": 5, + "cpld_device": "urukul0_cpld", + } + }, + "urukul0_ch2": { + "type": "local", + "module": "artiq.coredevice.ad9910", + "class": "AD9910", + "arguments": { + "pll_n": 32, + "chip_select": 6, + "cpld_device": "urukul0_cpld", + } + }, + "urukul0_ch3": { + "type": "local", + "module": "artiq.coredevice.ad9910", + "class": "AD9910", + "arguments": { + "pll_n": 32, + "chip_select": 7, + "cpld_device": "urukul0_cpld", + } + }, + + + + "spi_urukul1": { + "type": "local", + "module": "artiq.coredevice.spi2", + "class": "SPIMaster", + "arguments": {"channel": 17} + }, + "ttl_urukul1_io_update": { + "type": "local", + "module": "artiq.coredevice.ttl", + "class": "TTLOut", + "arguments": {"channel": 18} + }, + "urukul1_cpld": { + "type": "local", + "module": "artiq.coredevice.urukul", + "class": "CPLD", + "arguments": { + "spi_device": "spi_urukul1", + "io_update_device": "ttl_urukul1_io_update", + "refclk": 125e6, + "clk_sel": 1 + } + }, + "urukul1_ch0": { + "type": "local", + "module": "artiq.coredevice.ad9910", + "class": "AD9910", + "arguments": { + "pll_n": 32, + "chip_select": 4, + "cpld_device": "urukul1_cpld", + } + }, + "urukul1_ch1": { + "type": "local", + "module": "artiq.coredevice.ad9910", + "class": "AD9910", + "arguments": { + "pll_n": 32, + "chip_select": 5, + "cpld_device": "urukul1_cpld", + } + }, + "urukul1_ch2": { + "type": "local", + "module": "artiq.coredevice.ad9910", + "class": "AD9910", + "arguments": { + "pll_n": 32, + "chip_select": 6, + "cpld_device": "urukul1_cpld", + } + }, + "urukul1_ch3": { + "type": "local", + "module": "artiq.coredevice.ad9910", + "class": "AD9910", + "arguments": { + "pll_n": 32, + "chip_select": 7, + "cpld_device": "urukul1_cpld", + } + }, +} \ No newline at end of file diff --git a/experiments/mandelbrot.py b/experiments/mandelbrot.py new file mode 100755 index 0000000..70d20b4 --- /dev/null +++ b/experiments/mandelbrot.py @@ -0,0 +1,46 @@ +from artiq.experiment import * +import numpy as np + +class Mandelbrot(EnvExperiment): + def build(self): + self.setattr_device("core") + + def col(self, i): + sys.stdout.write(" .,-:;i+hHM$*#@ "[i]) + + def row(self): + print("") + + # based on: http://warp.povusers.org/MandScripts/python.html + @kernel + def run(self): + minX = -2.0 + maxX = 1.0 + width = 78 + height = 36 + aspectRatio = 2 + + yScale = (maxX-minX)*(height/width)*aspectRatio + + accum = 0. + + t0 = self.core.get_rtio_counter_mu() + + for y in range(height): + for x in range(width): + c_r = minX+x*(maxX-minX)/width + c_i = y*yScale/height-yScale/2 + z_r = c_r + z_i = c_i + i = 0 + for i in range(16): + if z_r*z_r + z_i*z_i > 4: + break + new_z_r = (z_r*z_r)-(z_i*z_i) + c_r + z_i = 2*z_r*z_i + c_i + z_r = new_z_r + accum += i + + dt = self.core.get_rtio_counter_mu() - t0 + core_log("Execution time:", np.int32(dt), "mu") + # Takes 666763336 mu on Kasli \ No newline at end of file diff --git a/experiments/minimal.py b/experiments/minimal.py new file mode 100755 index 0000000..16817ea --- /dev/null +++ b/experiments/minimal.py @@ -0,0 +1,14 @@ +from artiq.experiment import * + + +class Minimal(EnvExperiment): + def build(self): + self.setattr_device("core") + + @kernel + def run(self): + core_log(" :: Hello from kernel") + # try: + raise ValueError + # except ValueError as e: + # core_log(" :: Caught exception.") diff --git a/experiments/ttl.py b/experiments/ttl.py new file mode 100755 index 0000000..454182c --- /dev/null +++ b/experiments/ttl.py @@ -0,0 +1,93 @@ +from artiq.experiment import * +import numpy as np + +class TtlTests(EnvExperiment): + def build(self): + self.setattr_device("core") + self.ttlio = self.get_device("ttl0") + + @kernel + def bisect_underflow(self, f, t_max_mu=1000, t_min_mu=0): + t = 0 + while (t_max_mu-t_min_mu) > 1: + t = np.int64( (t_max_mu+t_min_mu)/2 ) + print(np.int32(t_min_mu), np.int32(t_max_mu)) + try: + f(t) + except RTIOUnderflow: + print("Underflow") + if t == t_max_mu: + raise ValueError("Upper bound underflowed") + t_min_mu = t + else: + t_max_mu = t + return t + + @kernel + def test_input_operation(self): + core_log("") + core_log("Test input operation ...") + self.core.reset() + self.ttlio.output() + delay(10*us) + with parallel: + self.ttlio.gate_rising(10*us) + with sequential: + delay(1*us) + t_out_mu = now_mu() + self.ttlio.pulse(1*us) + t_in_mu = self.ttlio.timestamp_mu() + dt = np.int32(t_in_mu-t_out_mu) + core_log("t_in-t_out:", dt, "mu") + + + @kernel + def event_response(self): + """How soon after an input event can we reliably schedule an output event""" + core_log("") + core_log("Measuring minimum event response time") + t = 0 + def f(t_delay): + self.core.reset() + + self.ttlio.output() + delay(1*us) + for i in range(10): + # Make sure we have plenty of slack + delay(1000*us) + self.ttlio.off() + delay(1*us) + with parallel: + self.ttlio.gate_rising(4*us) + with sequential: + delay(100*ns) + self.ttlio.pulse(100*ns) + + t_input = self.ttlio.timestamp_mu() + at_mu(t_input+t_delay) + self.ttlio.pulse(10*us) + t = self.bisect_underflow(lambda t: f(t), t_max_mu=10000) + core_log("Event response time: ", np.int32(t), "mu") + + @kernel + def output_pulse_rate(self): + """Sustained TTL output pulse rate""" + core_log("") + core_log("Measuring sustained output pulse rate") + t=0 + def f(t): + self.core.break_realtime() + for i in range(20000): + delay_mu(t) + self.ttlio.pulse_mu(t) + t = self.bisect_underflow(lambda t: f(t), t_max_mu=1000) + core_log("Sustained pulse rate: ", np.int32(2*t), "mu") + + + + @kernel + def run(self): + self.core.reset() + self.test_input_operation() + self.output_pulse_rate() + self.event_response() diff --git a/experiments/wall_time.py b/experiments/wall_time.py new file mode 100755 index 0000000..03adb26 --- /dev/null +++ b/experiments/wall_time.py @@ -0,0 +1,18 @@ +from artiq.experiment import * + +class WallTime(EnvExperiment): + def build(self): + self.setattr_device("core") + + @kernel + def run(self): + t0 = self.core.get_rtio_counter_mu() + i = 0 + while True: + t = self.core.get_rtio_counter_mu() + dt_s = (t-t0) + if dt_s < 1e9: + continue + t0 = t + core_log(i) + i += 1 \ No newline at end of file diff --git a/firmware/Cargo.toml b/firmware/Cargo.toml new file mode 100755 index 0000000..1673f0e --- /dev/null +++ b/firmware/Cargo.toml @@ -0,0 +1,7 @@ +[workspace] +members = ["runtime"] + +[profile.dev] +incremental = true +lto = false +opt-level = 2 \ No newline at end of file diff --git a/firmware/libboard_misoc/Cargo.toml b/firmware/libboard_misoc/Cargo.toml new file mode 100755 index 0000000..6b11faa --- /dev/null +++ b/firmware/libboard_misoc/Cargo.toml @@ -0,0 +1,14 @@ +[package] +name = "board_misoc" +version = "0.1.0" +authors = ["cjb "] + + + + +[dependencies] + +[lib] +path="lib.rs" +name = "board_misoc" + diff --git a/firmware/libboard_misoc/lib.rs b/firmware/libboard_misoc/lib.rs new file mode 100755 index 0000000..c57be85 --- /dev/null +++ b/firmware/libboard_misoc/lib.rs @@ -0,0 +1,56 @@ +#![no_std] +#![feature(asm)] + +include!(concat!(env!("BUILDINC_DIRECTORY"), "/generated/csr.rs")); + +pub mod uart; +#[macro_use] +pub mod uart_console; + +// Clean = expunge cache line with writeback +pub fn clean_data_cache(base: usize, len: usize) { + const CACHE_SYNC_OFFSET: isize = 0x0730/4; // Cache Sync + const CACHE_CLEAN_PA_OFFSET: isize = 0x7B0/4; + const L2CC_BASE: *mut u32 = 0xF8F02000 as *mut u32; + const CACHE_LINE_LENGTH: usize = 32; + let mut addr = base & !(CACHE_LINE_LENGTH-1); + loop { + if addr > base+len {break} + unsafe { + write_volatile(L2CC_BASE.offset(CACHE_CLEAN_PA_OFFSET), addr as u32); + write_volatile(L2CC_BASE.offset(CACHE_SYNC_OFFSET), 0); + + // Clean data cache line by virtual address + asm!("mcr p15, 0, $0, c7, c10, 1"::"r"(addr)) + } + addr += CACHE_LINE_LENGTH; + } +} + + +use core::ptr::write_volatile; + +// Invalidate = expunge cache line without writeback +pub fn invalidate_data_cache(base: usize, len: usize) { + const CACHE_SYNC_OFFSET: isize = 0x0730/4; // Cache Sync + const CACHE_INVLD_PA_OFFSET: isize = 0x0770/4; // Cache Invalid by PA + const L2CC_BASE: *mut u32 = 0xF8F02000 as *mut u32; + const CACHE_LINE_LENGTH: usize = 32; + + let mut addr = base & !(CACHE_LINE_LENGTH-1); + loop { + if addr > base+len {break} + + unsafe { + write_volatile(L2CC_BASE.offset(CACHE_INVLD_PA_OFFSET), addr as u32); + write_volatile(L2CC_BASE.offset(CACHE_SYNC_OFFSET), 0); + + // Invalidate data cache line by virtual address + asm!("mcr p15, 0, $0, c7, c6, 1"::"r"(addr)) + } + addr += CACHE_LINE_LENGTH; + } +} + + + diff --git a/firmware/libboard_misoc/uart.rs b/firmware/libboard_misoc/uart.rs new file mode 100755 index 0000000..0ed0a0f --- /dev/null +++ b/firmware/libboard_misoc/uart.rs @@ -0,0 +1,14 @@ +use core::ptr::{read_volatile, write_volatile}; + + +pub const UART_BASE: *mut u32 = 0xE0001000 as *mut u32; +// pub const UART_BASE: *mut u32 = 0x101000 as *mut u32; + + +#[export_name="uart_write"] +pub extern fn write(c: u8) { + unsafe { + while read_volatile(UART_BASE.offset(0x2c/4)) & 0x10 != 0 {} + write_volatile(UART_BASE.offset(0x30/4), c as u32); + } +} \ No newline at end of file diff --git a/firmware/libboard_misoc/uart_console.rs b/firmware/libboard_misoc/uart_console.rs new file mode 100755 index 0000000..f1545ef --- /dev/null +++ b/firmware/libboard_misoc/uart_console.rs @@ -0,0 +1,30 @@ +use core::fmt; + + +pub struct Console; + +impl fmt::Write for Console { + fn write_str(&mut self, s: &str) -> Result<(), fmt::Error> { + use uart; + + for c in s.bytes() { + unsafe { uart::write(c) } + } + + Ok(()) + } +} + +#[macro_export] +macro_rules! print { + ($($arg:tt)*) => ({ + use core::fmt::Write; + write!($crate::uart_console::Console, $($arg)*).unwrap() + }) +} + +#[macro_export] +macro_rules! println { + ($fmt:expr) => (print!(concat!($fmt, "\n"))); + ($fmt:expr, $($arg:tt)*) => (print!(concat!($fmt, "\n"), $($arg)*)); +} diff --git a/firmware/libdyld/Cargo.toml b/firmware/libdyld/Cargo.toml new file mode 100644 index 0000000..64c97c0 --- /dev/null +++ b/firmware/libdyld/Cargo.toml @@ -0,0 +1,8 @@ +[package] +authors = ["M-Labs"] +name = "dyld" +version = "0.0.0" + +[lib] +name = "dyld" +path = "lib.rs" diff --git a/firmware/libdyld/elf.rs b/firmware/libdyld/elf.rs new file mode 100644 index 0000000..0385bc7 --- /dev/null +++ b/firmware/libdyld/elf.rs @@ -0,0 +1,2737 @@ +/* generated from elf.h with rust-bindgen and then manually altered */ +#![allow(non_camel_case_types, non_snake_case, non_upper_case_globals)] + +pub const EI_NIDENT: usize = 16; +pub const EI_MAG0: usize = 0; +pub const ELFMAG0: u8 = 127; +pub const EI_MAG1: usize = 1; +pub const ELFMAG1: u8 = b'E'; +pub const EI_MAG2: usize = 2; +pub const ELFMAG2: u8 = b'L'; +pub const EI_MAG3: usize = 3; +pub const ELFMAG3: u8 = b'F'; +pub const ELFMAG: &'static [u8; 5usize] = b"\x7fELF\x00"; +pub const SELFMAG: usize = 4; +pub const EI_CLASS: usize = 4; +pub const ELFCLASSNONE: u8 = 0; +pub const ELFCLASS32: u8 = 1; +pub const ELFCLASS64: u8 = 2; +pub const ELFCLASSNUM: u8 = 3; +pub const EI_DATA: usize = 5; +pub const ELFDATANONE: u8 = 0; +pub const ELFDATA2LSB: u8 = 1; +pub const ELFDATA2MSB: u8 = 2; +pub const ELFDATANUM: u8 = 3; +pub const EI_VERSION: usize = 6; +pub const EI_OSABI: usize = 7; +pub const ELFOSABI_NONE: u8 = 0; +pub const ELFOSABI_SYSV: u8 = 0; +pub const ELFOSABI_HPUX: u8 = 1; +pub const ELFOSABI_NETBSD: u8 = 2; +pub const ELFOSABI_GNU: u8 = 3; +pub const ELFOSABI_LINUX: u8 = 3; +pub const ELFOSABI_SOLARIS: u8 = 6; +pub const ELFOSABI_AIX: u8 = 7; +pub const ELFOSABI_IRIX: u8 = 8; +pub const ELFOSABI_FREEBSD: u8 = 9; +pub const ELFOSABI_TRU64: u8 = 10; +pub const ELFOSABI_MODESTO: u8 = 11; +pub const ELFOSABI_OPENBSD: u8 = 12; +pub const ELFOSABI_ARM_AEABI: u8 = 64; +pub const ELFOSABI_ARM: u8 = 97; +pub const ELFOSABI_STANDALONE: u8 = 255; +pub const EI_ABIVERSION: usize = 8; +pub const EI_PAD: usize = 9; +pub const ET_NONE: u16 = 0; +pub const ET_REL: u16 = 1; +pub const ET_EXEC: u16 = 2; +pub const ET_DYN: u16 = 3; +pub const ET_CORE: u16 = 4; +pub const ET_NUM: u16 = 5; +pub const ET_LOOS: u16 = 65024; +pub const ET_HIOS: u16 = 65279; +pub const ET_LOPROC: u16 = 65280; +pub const ET_HIPROC: u16 = 65535; +pub const EM_NONE: u16 = 0; +pub const EM_M32: u16 = 1; +pub const EM_SPARC: u16 = 2; +pub const EM_386: u16 = 3; +pub const EM_68K: u16 = 4; +pub const EM_88K: u16 = 5; +pub const EM_860: u16 = 7; +pub const EM_MIPS: u16 = 8; +pub const EM_S370: u16 = 9; +pub const EM_MIPS_RS3_LE: u16 = 10; +pub const EM_PARISC: u16 = 15; +pub const EM_VPP500: u16 = 17; +pub const EM_SPARC32PLUS: u16 = 18; +pub const EM_960: u16 = 19; +pub const EM_PPC: u16 = 20; +pub const EM_PPC64: u16 = 21; +pub const EM_S390: u16 = 22; +pub const EM_V800: u16 = 36; +pub const EM_FR20: u16 = 37; +pub const EM_RH32: u16 = 38; +pub const EM_RCE: u16 = 39; +pub const EM_ARM: u16 = 40; +pub const EM_FAKE_ALPHA: u16 = 41; +pub const EM_SH: u16 = 42; +pub const EM_SPARCV9: u16 = 43; +pub const EM_TRICORE: u16 = 44; +pub const EM_ARC: u16 = 45; +pub const EM_H8_300: u16 = 46; +pub const EM_H8_300H: u16 = 47; +pub const EM_H8S: u16 = 48; +pub const EM_H8_500: u16 = 49; +pub const EM_IA_64: u16 = 50; +pub const EM_MIPS_X: u16 = 51; +pub const EM_COLDFIRE: u16 = 52; +pub const EM_68HC12: u16 = 53; +pub const EM_MMA: u16 = 54; +pub const EM_PCP: u16 = 55; +pub const EM_NCPU: u16 = 56; +pub const EM_NDR1: u16 = 57; +pub const EM_STARCORE: u16 = 58; +pub const EM_ME16: u16 = 59; +pub const EM_ST100: u16 = 60; +pub const EM_TINYJ: u16 = 61; +pub const EM_X86_64: u16 = 62; +pub const EM_PDSP: u16 = 63; +pub const EM_FX66: u16 = 66; +pub const EM_ST9PLUS: u16 = 67; +pub const EM_ST7: u16 = 68; +pub const EM_68HC16: u16 = 69; +pub const EM_68HC11: u16 = 70; +pub const EM_68HC08: u16 = 71; +pub const EM_68HC05: u16 = 72; +pub const EM_SVX: u16 = 73; +pub const EM_ST19: u16 = 74; +pub const EM_VAX: u16 = 75; +pub const EM_CRIS: u16 = 76; +pub const EM_JAVELIN: u16 = 77; +pub const EM_FIREPATH: u16 = 78; +pub const EM_ZSP: u16 = 79; +pub const EM_MMIX: u16 = 80; +pub const EM_HUANY: u16 = 81; +pub const EM_PRISM: u16 = 82; +pub const EM_AVR: u16 = 83; +pub const EM_FR30: u16 = 84; +pub const EM_D10V: u16 = 85; +pub const EM_D30V: u16 = 86; +pub const EM_V850: u16 = 87; +pub const EM_M32R: u16 = 88; +pub const EM_MN10300: u16 = 89; +pub const EM_MN10200: u16 = 90; +pub const EM_PJ: u16 = 91; +pub const EM_OPENRISC: u16 = 92; +pub const EM_ARC_A5: u16 = 93; +pub const EM_XTENSA: u16 = 94; +pub const EM_AARCH64: u16 = 183; +pub const EM_TILEPRO: u16 = 188; +pub const EM_MICROBLAZE: u16 = 189; +pub const EM_TILEGX: u16 = 191; +pub const EM_NUM: u16 = 192; +pub const EM_ALPHA: u16 = 36902; +pub const EV_NONE: u8 = 0; +pub const EV_CURRENT: u8 = 1; +pub const EV_NUM: u8 = 2; +pub const SHN_UNDEF: u16 = 0; +pub const SHN_LORESERVE: u16 = 65280; +pub const SHN_LOPROC: u16 = 65280; +pub const SHN_BEFORE: u16 = 65280; +pub const SHN_AFTER: u16 = 65281; +pub const SHN_HIPROC: u16 = 65311; +pub const SHN_LOOS: u16 = 65312; +pub const SHN_HIOS: u16 = 65343; +pub const SHN_ABS: u16 = 65521; +pub const SHN_COMMON: u16 = 65522; +pub const SHN_XINDEX: u16 = 65535; +pub const SHN_HIRESERVE: u16 = 65535; +pub const SHT_NULL: usize = 0; +pub const SHT_PROGBITS: usize = 1; +pub const SHT_SYMTAB: usize = 2; +pub const SHT_STRTAB: usize = 3; +pub const SHT_RELA: usize = 4; +pub const SHT_HASH: usize = 5; +pub const SHT_DYNAMIC: usize = 6; +pub const SHT_NOTE: usize = 7; +pub const SHT_NOBITS: usize = 8; +pub const SHT_REL: usize = 9; +pub const SHT_SHLIB: usize = 10; +pub const SHT_DYNSYM: usize = 11; +pub const SHT_INIT_ARRAY: usize = 14; +pub const SHT_FINI_ARRAY: usize = 15; +pub const SHT_PREINIT_ARRAY: usize = 16; +pub const SHT_GROUP: usize = 17; +pub const SHT_SYMTAB_SHNDX: usize = 18; +pub const SHT_NUM: usize = 19; +pub const SHT_LOOS: usize = 1610612736; +pub const SHT_GNU_ATTRIBUTES: usize = 1879048181; +pub const SHT_GNU_HASH: usize = 1879048182; +pub const SHT_GNU_LIBLIST: usize = 1879048183; +pub const SHT_CHECKSUM: usize = 1879048184; +pub const SHT_LOSUNW: usize = 1879048186; +pub const SHT_SUNW_move: usize = 1879048186; +pub const SHT_SUNW_COMDAT: usize = 1879048187; +pub const SHT_SUNW_syminfo: usize = 1879048188; +pub const SHT_GNU_verdef: usize = 1879048189; +pub const SHT_GNU_verneed: usize = 1879048190; +pub const SHT_GNU_versym: usize = 1879048191; +pub const SHT_HISUNW: usize = 1879048191; +pub const SHT_HIOS: usize = 1879048191; +pub const SHT_LOPROC: usize = 1879048192; +pub const SHT_HIPROC: usize = 2147483647; +pub const SHT_LOUSER: usize = 2147483648; +pub const SHT_HIUSER: usize = 2415919103; +pub const SHF_WRITE: usize = 1; +pub const SHF_ALLOC: usize = 2; +pub const SHF_EXECINSTR: usize = 4; +pub const SHF_MERGE: usize = 16; +pub const SHF_STRINGS: usize = 32; +pub const SHF_INFO_LINK: usize = 64; +pub const SHF_LINK_ORDER: usize = 128; +pub const SHF_OS_NONCONFORMING: usize = 256; +pub const SHF_GROUP: usize = 512; +pub const SHF_TLS: usize = 1024; +pub const SHF_MASKOS: usize = 267386880; +pub const SHF_MASKPROC: usize = 4026531840; +pub const SHF_ORDERED: usize = 1073741824; +pub const SHF_EXCLUDE: usize = 2147483648; +pub const GRP_COMDAT: usize = 1; +pub const SYMINFO_BT_SELF: usize = 65535; +pub const SYMINFO_BT_PARENT: usize = 65534; +pub const SYMINFO_BT_LOWRESERVE: usize = 65280; +pub const SYMINFO_FLG_DIRECT: usize = 1; +pub const SYMINFO_FLG_PASSTHRU: usize = 2; +pub const SYMINFO_FLG_COPY: usize = 4; +pub const SYMINFO_FLG_LAZYLOAD: usize = 8; +pub const SYMINFO_NONE: usize = 0; +pub const SYMINFO_CURRENT: usize = 1; +pub const SYMINFO_NUM: usize = 2; +pub const STB_LOCAL: u8 = 0; +pub const STB_GLOBAL: u8 = 1; +pub const STB_WEAK: u8 = 2; +pub const STB_NUM: u8 = 3; +pub const STB_LOOS: u8 = 10; +pub const STB_GNU_UNIQUE: u8 = 10; +pub const STB_HIOS: u8 = 12; +pub const STB_LOPROC: u8 = 13; +pub const STB_HIPROC: u8 = 15; +pub const STT_NOTYPE: u8 = 0; +pub const STT_OBJECT: u8 = 1; +pub const STT_FUNC: u8 = 2; +pub const STT_SECTION: u8 = 3; +pub const STT_FILE: u8 = 4; +pub const STT_COMMON: u8 = 5; +pub const STT_TLS: u8 = 6; +pub const STT_NUM: u8 = 7; +pub const STT_LOOS: u8 = 10; +pub const STT_GNU_IFUNC: u8 = 10; +pub const STT_HIOS: u8 = 12; +pub const STT_LOPROC: u8 = 13; +pub const STT_HIPROC: u8 = 15; +pub const STN_UNDEF: usize = 0; +pub const STV_DEFAULT: usize = 0; +pub const STV_INTERNAL: usize = 1; +pub const STV_HIDDEN: usize = 2; +pub const STV_PROTECTED: usize = 3; +pub const PN_XNUM: usize = 65535; +pub const PT_NULL: u32 = 0; +pub const PT_LOAD: u32 = 1; +pub const PT_DYNAMIC: u32 = 2; +pub const PT_INTERP: u32 = 3; +pub const PT_NOTE: u32 = 4; +pub const PT_SHLIB: u32 = 5; +pub const PT_PHDR: u32 = 6; +pub const PT_TLS: u32 = 7; +pub const PT_NUM: u32 = 8; +pub const PT_LOOS: u32 = 1610612736; +pub const PT_GNU_EH_FRAME: u32 = 1685382480; +pub const PT_GNU_STACK: u32 = 1685382481; +pub const PT_GNU_RELRO: u32 = 1685382482; +pub const PT_LOSUNW: u32 = 1879048186; +pub const PT_SUNWBSS: u32 = 1879048186; +pub const PT_SUNWSTACK: u32 = 1879048187; +pub const PT_HISUNW: u32 = 1879048191; +pub const PT_HIOS: u32 = 1879048191; +pub const PT_LOPROC: u32 = 1879048192; +pub const PT_HIPROC: u32 = 2147483647; +pub const PF_X: usize = 1; +pub const PF_W: usize = 2; +pub const PF_R: usize = 4; +pub const PF_MASKOS: usize = 267386880; +pub const PF_MASKPROC: usize = 4026531840; +pub const NT_PRSTATUS: usize = 1; +pub const NT_FPREGSET: usize = 2; +pub const NT_PRPSINFO: usize = 3; +pub const NT_PRXREG: usize = 4; +pub const NT_TASKSTRUCT: usize = 4; +pub const NT_PLATFORM: usize = 5; +pub const NT_AUXV: usize = 6; +pub const NT_GWINDOWS: usize = 7; +pub const NT_ASRS: usize = 8; +pub const NT_PSTATUS: usize = 10; +pub const NT_PSINFO: usize = 13; +pub const NT_PRCRED: usize = 14; +pub const NT_UTSNAME: usize = 15; +pub const NT_LWPSTATUS: usize = 16; +pub const NT_LWPSINFO: usize = 17; +pub const NT_PRFPXREG: usize = 20; +pub const NT_SIGINFO: usize = 1397311305; +pub const NT_FILE: usize = 1179208773; +pub const NT_PRXFPREG: usize = 1189489535; +pub const NT_PPC_VMX: usize = 256; +pub const NT_PPC_SPE: usize = 257; +pub const NT_PPC_VSX: usize = 258; +pub const NT_386_TLS: usize = 512; +pub const NT_386_IOPERM: usize = 513; +pub const NT_X86_XSTATE: usize = 514; +pub const NT_S390_HIGH_GPRS: usize = 768; +pub const NT_S390_TIMER: usize = 769; +pub const NT_S390_TODCMP: usize = 770; +pub const NT_S390_TODPREG: usize = 771; +pub const NT_S390_CTRS: usize = 772; +pub const NT_S390_PREFIX: usize = 773; +pub const NT_S390_LAST_BREAK: usize = 774; +pub const NT_S390_SYSTEM_CALL: usize = 775; +pub const NT_S390_TDB: usize = 776; +pub const NT_ARM_VFP: usize = 1024; +pub const NT_ARM_TLS: usize = 1025; +pub const NT_ARM_HW_BREAK: usize = 1026; +pub const NT_ARM_HW_WATCH: usize = 1027; +pub const NT_VERSION: usize = 1; +pub const DT_NULL: i32 = 0; +pub const DT_NEEDED: i32 = 1; +pub const DT_PLTRELSZ: i32 = 2; +pub const DT_PLTGOT: i32 = 3; +pub const DT_HASH: i32 = 4; +pub const DT_STRTAB: i32 = 5; +pub const DT_SYMTAB: i32 = 6; +pub const DT_RELA: i32 = 7; +pub const DT_RELASZ: i32 = 8; +pub const DT_RELAENT: i32 = 9; +pub const DT_STRSZ: i32 = 10; +pub const DT_SYMENT: i32 = 11; +pub const DT_INIT: i32 = 12; +pub const DT_FINI: i32 = 13; +pub const DT_SONAME: i32 = 14; +pub const DT_RPATH: i32 = 15; +pub const DT_SYMBOLIC: i32 = 16; +pub const DT_REL: i32 = 17; +pub const DT_RELSZ: i32 = 18; +pub const DT_RELENT: i32 = 19; +pub const DT_PLTREL: i32 = 20; +pub const DT_DEBUG: i32 = 21; +pub const DT_TEXTREL: i32 = 22; +pub const DT_JMPREL: i32 = 23; +pub const DT_BIND_NOW: i32 = 24; +pub const DT_INIT_ARRAY: i32 = 25; +pub const DT_FINI_ARRAY: i32 = 26; +pub const DT_INIT_ARRAYSZ: i32 = 27; +pub const DT_FINI_ARRAYSZ: i32 = 28; +pub const DT_RUNPATH: i32 = 29; +pub const DT_FLAGS: i32 = 30; +pub const DT_ENCODING: i32 = 32; +pub const DT_PREINIT_ARRAY: i32 = 32; +pub const DT_PREINIT_ARRAYSZ: i32 = 33; +pub const DT_NUM: i32 = 34; +pub const DT_LOOS: i32 = 1610612749; +pub const DT_HIOS: i32 = 1879044096; +pub const DT_LOPROC: i32 = 1879048192; +pub const DT_HIPROC: i32 = 2147483647; +pub const DT_VALRNGLO: i32 = 1879047424; +pub const DT_GNU_PRELINKED: i32 = 1879047669; +pub const DT_GNU_CONFLICTSZ: i32 = 1879047670; +pub const DT_GNU_LIBLISTSZ: i32 = 1879047671; +pub const DT_CHECKSUM: i32 = 1879047672; +pub const DT_PLTPADSZ: i32 = 1879047673; +pub const DT_MOVEENT: i32 = 1879047674; +pub const DT_MOVESZ: i32 = 1879047675; +pub const DT_FEATURE_1: i32 = 1879047676; +pub const DT_POSFLAG_1: i32 = 1879047677; +pub const DT_SYMINSZ: i32 = 1879047678; +pub const DT_SYMINENT: i32 = 1879047679; +pub const DT_VALRNGHI: i32 = 1879047679; +pub const DT_VALNUM: i32 = 12; +pub const DT_ADDRRNGLO: i32 = 1879047680; +pub const DT_GNU_HASH: i32 = 1879047925; +pub const DT_TLSDESC_PLT: i32 = 1879047926; +pub const DT_TLSDESC_GOT: i32 = 1879047927; +pub const DT_GNU_CONFLICT: i32 = 1879047928; +pub const DT_GNU_LIBLIST: i32 = 1879047929; +pub const DT_CONFIG: i32 = 1879047930; +pub const DT_DEPAUDIT: i32 = 1879047931; +pub const DT_AUDIT: i32 = 1879047932; +pub const DT_PLTPAD: i32 = 1879047933; +pub const DT_MOVETAB: i32 = 1879047934; +pub const DT_SYMINFO: i32 = 1879047935; +pub const DT_ADDRRNGHI: i32 = 1879047935; +pub const DT_ADDRNUM: i32 = 11; +pub const DT_VERSYM: i32 = 1879048176; +pub const DT_RELACOUNT: i32 = 1879048185; +pub const DT_RELCOUNT: i32 = 1879048186; +pub const DT_FLAGS_1: i32 = 1879048187; +pub const DT_VERDEF: i32 = 1879048188; +pub const DT_VERDEFNUM: i32 = 1879048189; +pub const DT_VERNEED: i32 = 1879048190; +pub const DT_VERNEEDNUM: i32 = 1879048191; +pub const DT_VERSIONTAGNUM: i32 = 16; +pub const DT_AUXILIARY: i32 = 2147483645; +pub const DT_FILTER: i32 = 2147483647; +pub const DT_EXTRANUM: i32 = 3; +pub const DF_ORIGIN: usize = 1; +pub const DF_SYMBOLIC: usize = 2; +pub const DF_TEXTREL: usize = 4; +pub const DF_BIND_NOW: usize = 8; +pub const DF_STATIC_TLS: usize = 16; +pub const DF_1_NOW: usize = 1; +pub const DF_1_GLOBAL: usize = 2; +pub const DF_1_GROUP: usize = 4; +pub const DF_1_NODELETE: usize = 8; +pub const DF_1_LOADFLTR: usize = 16; +pub const DF_1_INITFIRST: usize = 32; +pub const DF_1_NOOPEN: usize = 64; +pub const DF_1_ORIGIN: usize = 128; +pub const DF_1_DIRECT: usize = 256; +pub const DF_1_TRANS: usize = 512; +pub const DF_1_INTERPOSE: usize = 1024; +pub const DF_1_NODEFLIB: usize = 2048; +pub const DF_1_NODUMP: usize = 4096; +pub const DF_1_CONFALT: usize = 8192; +pub const DF_1_ENDFILTEE: usize = 16384; +pub const DF_1_DISPRELDNE: usize = 32768; +pub const DF_1_DISPRELPND: usize = 65536; +pub const DF_1_NODIRECT: usize = 131072; +pub const DF_1_IGNMULDEF: usize = 262144; +pub const DF_1_NOKSYMS: usize = 524288; +pub const DF_1_NOHDR: usize = 1048576; +pub const DF_1_EDITED: usize = 2097152; +pub const DF_1_NORELOC: usize = 4194304; +pub const DF_1_SYMINTPOSE: usize = 8388608; +pub const DF_1_GLOBAUDIT: usize = 16777216; +pub const DF_1_SINGLETON: usize = 33554432; +pub const DTF_1_PARINIT: usize = 1; +pub const DTF_1_CONFEXP: usize = 2; +pub const DF_P1_LAZYLOAD: usize = 1; +pub const DF_P1_GROUPPERM: usize = 2; +pub const VER_DEF_NONE: usize = 0; +pub const VER_DEF_CURRENT: usize = 1; +pub const VER_DEF_NUM: usize = 2; +pub const VER_FLG_BASE: usize = 1; +pub const VER_FLG_WEAK: usize = 2; +pub const VER_NDX_LOCAL: usize = 0; +pub const VER_NDX_GLOBAL: usize = 1; +pub const VER_NDX_LORESERVE: usize = 65280; +pub const VER_NDX_ELIMINATE: usize = 65281; +pub const VER_NEED_NONE: usize = 0; +pub const VER_NEED_CURRENT: usize = 1; +pub const VER_NEED_NUM: usize = 2; +pub const ELF_NOTE_SOLARIS: &'static [u8; 13usize] = b"SUNW Solaris\x00"; +pub const ELF_NOTE_GNU: &'static [u8; 4usize] = b"GNU\x00"; +pub const ELF_NOTE_PAGESIZE_HINT: usize = 1; +pub const NT_GNU_ABI_TAG: usize = 1; +pub const ELF_NOTE_ABI: usize = 1; +pub const ELF_NOTE_OS_LINUX: usize = 0; +pub const ELF_NOTE_OS_GNU: usize = 1; +pub const ELF_NOTE_OS_SOLARIS2: usize = 2; +pub const ELF_NOTE_OS_FREEBSD: usize = 3; +pub const NT_GNU_HWCAP: usize = 2; +pub const NT_GNU_BUILD_ID: usize = 3; +pub const NT_GNU_GOLD_VERSION: usize = 4; +pub const EF_CPU32: usize = 8454144; +pub const R_68K_NONE: usize = 0; +pub const R_68K_32: usize = 1; +pub const R_68K_16: usize = 2; +pub const R_68K_8: usize = 3; +pub const R_68K_PC32: usize = 4; +pub const R_68K_PC16: usize = 5; +pub const R_68K_PC8: usize = 6; +pub const R_68K_GOT32: usize = 7; +pub const R_68K_GOT16: usize = 8; +pub const R_68K_GOT8: usize = 9; +pub const R_68K_GOT32O: usize = 10; +pub const R_68K_GOT16O: usize = 11; +pub const R_68K_GOT8O: usize = 12; +pub const R_68K_PLT32: usize = 13; +pub const R_68K_PLT16: usize = 14; +pub const R_68K_PLT8: usize = 15; +pub const R_68K_PLT32O: usize = 16; +pub const R_68K_PLT16O: usize = 17; +pub const R_68K_PLT8O: usize = 18; +pub const R_68K_COPY: usize = 19; +pub const R_68K_GLOB_DAT: usize = 20; +pub const R_68K_JMP_SLOT: usize = 21; +pub const R_68K_RELATIVE: usize = 22; +pub const R_68K_TLS_GD32: usize = 25; +pub const R_68K_TLS_GD16: usize = 26; +pub const R_68K_TLS_GD8: usize = 27; +pub const R_68K_TLS_LDM32: usize = 28; +pub const R_68K_TLS_LDM16: usize = 29; +pub const R_68K_TLS_LDM8: usize = 30; +pub const R_68K_TLS_LDO32: usize = 31; +pub const R_68K_TLS_LDO16: usize = 32; +pub const R_68K_TLS_LDO8: usize = 33; +pub const R_68K_TLS_IE32: usize = 34; +pub const R_68K_TLS_IE16: usize = 35; +pub const R_68K_TLS_IE8: usize = 36; +pub const R_68K_TLS_LE32: usize = 37; +pub const R_68K_TLS_LE16: usize = 38; +pub const R_68K_TLS_LE8: usize = 39; +pub const R_68K_TLS_DTPMOD32: usize = 40; +pub const R_68K_TLS_DTPREL32: usize = 41; +pub const R_68K_TLS_TPREL32: usize = 42; +pub const R_68K_NUM: usize = 43; +pub const R_386_NONE: usize = 0; +pub const R_386_32: usize = 1; +pub const R_386_PC32: usize = 2; +pub const R_386_GOT32: usize = 3; +pub const R_386_PLT32: usize = 4; +pub const R_386_COPY: usize = 5; +pub const R_386_GLOB_DAT: usize = 6; +pub const R_386_JMP_SLOT: usize = 7; +pub const R_386_RELATIVE: usize = 8; +pub const R_386_GOTOFF: usize = 9; +pub const R_386_GOTPC: usize = 10; +pub const R_386_32PLT: usize = 11; +pub const R_386_TLS_TPOFF: usize = 14; +pub const R_386_TLS_IE: usize = 15; +pub const R_386_TLS_GOTIE: usize = 16; +pub const R_386_TLS_LE: usize = 17; +pub const R_386_TLS_GD: usize = 18; +pub const R_386_TLS_LDM: usize = 19; +pub const R_386_16: usize = 20; +pub const R_386_PC16: usize = 21; +pub const R_386_8: usize = 22; +pub const R_386_PC8: usize = 23; +pub const R_386_TLS_GD_32: usize = 24; +pub const R_386_TLS_GD_PUSH: usize = 25; +pub const R_386_TLS_GD_CALL: usize = 26; +pub const R_386_TLS_GD_POP: usize = 27; +pub const R_386_TLS_LDM_32: usize = 28; +pub const R_386_TLS_LDM_PUSH: usize = 29; +pub const R_386_TLS_LDM_CALL: usize = 30; +pub const R_386_TLS_LDM_POP: usize = 31; +pub const R_386_TLS_LDO_32: usize = 32; +pub const R_386_TLS_IE_32: usize = 33; +pub const R_386_TLS_LE_32: usize = 34; +pub const R_386_TLS_DTPMOD32: usize = 35; +pub const R_386_TLS_DTPOFF32: usize = 36; +pub const R_386_TLS_TPOFF32: usize = 37; +pub const R_386_SIZE32: usize = 38; +pub const R_386_TLS_GOTDESC: usize = 39; +pub const R_386_TLS_DESC_CALL: usize = 40; +pub const R_386_TLS_DESC: usize = 41; +pub const R_386_IRELATIVE: usize = 42; +pub const R_386_NUM: usize = 43; +pub const STT_SPARC_REGISTER: usize = 13; +pub const EF_SPARCV9_MM: usize = 3; +pub const EF_SPARCV9_TSO: usize = 0; +pub const EF_SPARCV9_PSO: usize = 1; +pub const EF_SPARCV9_RMO: usize = 2; +pub const EF_SPARC_LEDATA: usize = 8388608; +pub const EF_SPARC_EXT_MASK: usize = 16776960; +pub const EF_SPARC_32PLUS: usize = 256; +pub const EF_SPARC_SUN_US1: usize = 512; +pub const EF_SPARC_HAL_R1: usize = 1024; +pub const EF_SPARC_SUN_US3: usize = 2048; +pub const R_SPARC_NONE: usize = 0; +pub const R_SPARC_8: usize = 1; +pub const R_SPARC_16: usize = 2; +pub const R_SPARC_32: usize = 3; +pub const R_SPARC_DISP8: usize = 4; +pub const R_SPARC_DISP16: usize = 5; +pub const R_SPARC_DISP32: usize = 6; +pub const R_SPARC_WDISP30: usize = 7; +pub const R_SPARC_WDISP22: usize = 8; +pub const R_SPARC_HI22: usize = 9; +pub const R_SPARC_22: usize = 10; +pub const R_SPARC_13: usize = 11; +pub const R_SPARC_LO10: usize = 12; +pub const R_SPARC_GOT10: usize = 13; +pub const R_SPARC_GOT13: usize = 14; +pub const R_SPARC_GOT22: usize = 15; +pub const R_SPARC_PC10: usize = 16; +pub const R_SPARC_PC22: usize = 17; +pub const R_SPARC_WPLT30: usize = 18; +pub const R_SPARC_COPY: usize = 19; +pub const R_SPARC_GLOB_DAT: usize = 20; +pub const R_SPARC_JMP_SLOT: usize = 21; +pub const R_SPARC_RELATIVE: usize = 22; +pub const R_SPARC_UA32: usize = 23; +pub const R_SPARC_PLT32: usize = 24; +pub const R_SPARC_HIPLT22: usize = 25; +pub const R_SPARC_LOPLT10: usize = 26; +pub const R_SPARC_PCPLT32: usize = 27; +pub const R_SPARC_PCPLT22: usize = 28; +pub const R_SPARC_PCPLT10: usize = 29; +pub const R_SPARC_10: usize = 30; +pub const R_SPARC_11: usize = 31; +pub const R_SPARC_64: usize = 32; +pub const R_SPARC_OLO10: usize = 33; +pub const R_SPARC_HH22: usize = 34; +pub const R_SPARC_HM10: usize = 35; +pub const R_SPARC_LM22: usize = 36; +pub const R_SPARC_PC_HH22: usize = 37; +pub const R_SPARC_PC_HM10: usize = 38; +pub const R_SPARC_PC_LM22: usize = 39; +pub const R_SPARC_WDISP16: usize = 40; +pub const R_SPARC_WDISP19: usize = 41; +pub const R_SPARC_GLOB_JMP: usize = 42; +pub const R_SPARC_7: usize = 43; +pub const R_SPARC_5: usize = 44; +pub const R_SPARC_6: usize = 45; +pub const R_SPARC_DISP64: usize = 46; +pub const R_SPARC_PLT64: usize = 47; +pub const R_SPARC_HIX22: usize = 48; +pub const R_SPARC_LOX10: usize = 49; +pub const R_SPARC_H44: usize = 50; +pub const R_SPARC_M44: usize = 51; +pub const R_SPARC_L44: usize = 52; +pub const R_SPARC_REGISTER: usize = 53; +pub const R_SPARC_UA64: usize = 54; +pub const R_SPARC_UA16: usize = 55; +pub const R_SPARC_TLS_GD_HI22: usize = 56; +pub const R_SPARC_TLS_GD_LO10: usize = 57; +pub const R_SPARC_TLS_GD_ADD: usize = 58; +pub const R_SPARC_TLS_GD_CALL: usize = 59; +pub const R_SPARC_TLS_LDM_HI22: usize = 60; +pub const R_SPARC_TLS_LDM_LO10: usize = 61; +pub const R_SPARC_TLS_LDM_ADD: usize = 62; +pub const R_SPARC_TLS_LDM_CALL: usize = 63; +pub const R_SPARC_TLS_LDO_HIX22: usize = 64; +pub const R_SPARC_TLS_LDO_LOX10: usize = 65; +pub const R_SPARC_TLS_LDO_ADD: usize = 66; +pub const R_SPARC_TLS_IE_HI22: usize = 67; +pub const R_SPARC_TLS_IE_LO10: usize = 68; +pub const R_SPARC_TLS_IE_LD: usize = 69; +pub const R_SPARC_TLS_IE_LDX: usize = 70; +pub const R_SPARC_TLS_IE_ADD: usize = 71; +pub const R_SPARC_TLS_LE_HIX22: usize = 72; +pub const R_SPARC_TLS_LE_LOX10: usize = 73; +pub const R_SPARC_TLS_DTPMOD32: usize = 74; +pub const R_SPARC_TLS_DTPMOD64: usize = 75; +pub const R_SPARC_TLS_DTPOFF32: usize = 76; +pub const R_SPARC_TLS_DTPOFF64: usize = 77; +pub const R_SPARC_TLS_TPOFF32: usize = 78; +pub const R_SPARC_TLS_TPOFF64: usize = 79; +pub const R_SPARC_GOTDATA_HIX22: usize = 80; +pub const R_SPARC_GOTDATA_LOX10: usize = 81; +pub const R_SPARC_GOTDATA_OP_HIX22: usize = 82; +pub const R_SPARC_GOTDATA_OP_LOX10: usize = 83; +pub const R_SPARC_GOTDATA_OP: usize = 84; +pub const R_SPARC_H34: usize = 85; +pub const R_SPARC_SIZE32: usize = 86; +pub const R_SPARC_SIZE64: usize = 87; +pub const R_SPARC_WDISP10: usize = 88; +pub const R_SPARC_JMP_IREL: usize = 248; +pub const R_SPARC_IRELATIVE: usize = 249; +pub const R_SPARC_GNU_VTINHERIT: usize = 250; +pub const R_SPARC_GNU_VTENTRY: usize = 251; +pub const R_SPARC_REV32: usize = 252; +pub const R_SPARC_NUM: usize = 253; +pub const DT_SPARC_REGISTER: usize = 1879048193; +pub const DT_SPARC_NUM: usize = 2; +pub const EF_MIPS_NOREORDER: usize = 1; +pub const EF_MIPS_PIC: usize = 2; +pub const EF_MIPS_CPIC: usize = 4; +pub const EF_MIPS_XGOT: usize = 8; +pub const EF_MIPS_64BIT_WHIRL: usize = 16; +pub const EF_MIPS_ABI2: usize = 32; +pub const EF_MIPS_ABI_ON32: usize = 64; +pub const EF_MIPS_NAN2008: usize = 1024; +pub const EF_MIPS_ARCH: usize = 4026531840; +pub const EF_MIPS_ARCH_1: usize = 0; +pub const EF_MIPS_ARCH_2: usize = 268435456; +pub const EF_MIPS_ARCH_3: usize = 536870912; +pub const EF_MIPS_ARCH_4: usize = 805306368; +pub const EF_MIPS_ARCH_5: usize = 1073741824; +pub const EF_MIPS_ARCH_32: usize = 1342177280; +pub const EF_MIPS_ARCH_64: usize = 1610612736; +pub const EF_MIPS_ARCH_32R2: usize = 1879048192; +pub const EF_MIPS_ARCH_64R2: usize = 2147483648; +pub const E_MIPS_ARCH_1: usize = 0; +pub const E_MIPS_ARCH_2: usize = 268435456; +pub const E_MIPS_ARCH_3: usize = 536870912; +pub const E_MIPS_ARCH_4: usize = 805306368; +pub const E_MIPS_ARCH_5: usize = 1073741824; +pub const E_MIPS_ARCH_32: usize = 1342177280; +pub const E_MIPS_ARCH_64: usize = 1610612736; +pub const SHN_MIPS_ACOMMON: usize = 65280; +pub const SHN_MIPS_TEXT: usize = 65281; +pub const SHN_MIPS_DATA: usize = 65282; +pub const SHN_MIPS_SCOMMON: usize = 65283; +pub const SHN_MIPS_SUNDEFINED: usize = 65284; +pub const SHT_MIPS_LIBLIST: usize = 1879048192; +pub const SHT_MIPS_MSYM: usize = 1879048193; +pub const SHT_MIPS_CONFLICT: usize = 1879048194; +pub const SHT_MIPS_GPTAB: usize = 1879048195; +pub const SHT_MIPS_UCODE: usize = 1879048196; +pub const SHT_MIPS_DEBUG: usize = 1879048197; +pub const SHT_MIPS_REGINFO: usize = 1879048198; +pub const SHT_MIPS_PACKAGE: usize = 1879048199; +pub const SHT_MIPS_PACKSYM: usize = 1879048200; +pub const SHT_MIPS_RELD: usize = 1879048201; +pub const SHT_MIPS_IFACE: usize = 1879048203; +pub const SHT_MIPS_CONTENT: usize = 1879048204; +pub const SHT_MIPS_OPTIONS: usize = 1879048205; +pub const SHT_MIPS_SHDR: usize = 1879048208; +pub const SHT_MIPS_FDESC: usize = 1879048209; +pub const SHT_MIPS_EXTSYM: usize = 1879048210; +pub const SHT_MIPS_DENSE: usize = 1879048211; +pub const SHT_MIPS_PDESC: usize = 1879048212; +pub const SHT_MIPS_LOCSYM: usize = 1879048213; +pub const SHT_MIPS_AUXSYM: usize = 1879048214; +pub const SHT_MIPS_OPTSYM: usize = 1879048215; +pub const SHT_MIPS_LOCSTR: usize = 1879048216; +pub const SHT_MIPS_LINE: usize = 1879048217; +pub const SHT_MIPS_RFDESC: usize = 1879048218; +pub const SHT_MIPS_DELTASYM: usize = 1879048219; +pub const SHT_MIPS_DELTAINST: usize = 1879048220; +pub const SHT_MIPS_DELTACLASS: usize = 1879048221; +pub const SHT_MIPS_DWARF: usize = 1879048222; +pub const SHT_MIPS_DELTADECL: usize = 1879048223; +pub const SHT_MIPS_SYMBOL_LIB: usize = 1879048224; +pub const SHT_MIPS_EVENTS: usize = 1879048225; +pub const SHT_MIPS_TRANSLATE: usize = 1879048226; +pub const SHT_MIPS_PIXIE: usize = 1879048227; +pub const SHT_MIPS_XLATE: usize = 1879048228; +pub const SHT_MIPS_XLATE_DEBUG: usize = 1879048229; +pub const SHT_MIPS_WHIRL: usize = 1879048230; +pub const SHT_MIPS_EH_REGION: usize = 1879048231; +pub const SHT_MIPS_XLATE_OLD: usize = 1879048232; +pub const SHT_MIPS_PDR_EXCEPTION: usize = 1879048233; +pub const SHF_MIPS_GPREL: usize = 268435456; +pub const SHF_MIPS_MERGE: usize = 536870912; +pub const SHF_MIPS_ADDR: usize = 1073741824; +pub const SHF_MIPS_STRINGS: usize = 2147483648; +pub const SHF_MIPS_NOSTRIP: usize = 134217728; +pub const SHF_MIPS_LOCAL: usize = 67108864; +pub const SHF_MIPS_NAMES: usize = 33554432; +pub const SHF_MIPS_NODUPE: usize = 16777216; +pub const STO_MIPS_DEFAULT: usize = 0; +pub const STO_MIPS_INTERNAL: usize = 1; +pub const STO_MIPS_HIDDEN: usize = 2; +pub const STO_MIPS_PROTECTED: usize = 3; +pub const STO_MIPS_PLT: usize = 8; +pub const STO_MIPS_SC_ALIGN_UNUSED: usize = 255; +pub const STB_MIPS_SPLIT_COMMON: usize = 13; +pub const ODK_NULL: usize = 0; +pub const ODK_REGINFO: usize = 1; +pub const ODK_EXCEPTIONS: usize = 2; +pub const ODK_PAD: usize = 3; +pub const ODK_HWPATCH: usize = 4; +pub const ODK_FILL: usize = 5; +pub const ODK_TAGS: usize = 6; +pub const ODK_HWAND: usize = 7; +pub const ODK_HWOR: usize = 8; +pub const OEX_FPU_MIN: usize = 31; +pub const OEX_FPU_MAX: usize = 7936; +pub const OEX_PAGE0: usize = 65536; +pub const OEX_SMM: usize = 131072; +pub const OEX_FPDBUG: usize = 262144; +pub const OEX_PRECISEFP: usize = 262144; +pub const OEX_DISMISS: usize = 524288; +pub const OEX_FPU_INVAL: usize = 16; +pub const OEX_FPU_DIV0: usize = 8; +pub const OEX_FPU_OFLO: usize = 4; +pub const OEX_FPU_UFLO: usize = 2; +pub const OEX_FPU_INEX: usize = 1; +pub const OHW_R4KEOP: usize = 1; +pub const OHW_R8KPFETCH: usize = 2; +pub const OHW_R5KEOP: usize = 4; +pub const OHW_R5KCVTL: usize = 8; +pub const OPAD_PREFIX: usize = 1; +pub const OPAD_POSTFIX: usize = 2; +pub const OPAD_SYMBOL: usize = 4; +pub const OHWA0_R4KEOP_CHECKED: usize = 1; +pub const OHWA1_R4KEOP_CLEAN: usize = 2; +pub const R_MIPS_NONE: usize = 0; +pub const R_MIPS_16: usize = 1; +pub const R_MIPS_32: usize = 2; +pub const R_MIPS_REL32: usize = 3; +pub const R_MIPS_26: usize = 4; +pub const R_MIPS_HI16: usize = 5; +pub const R_MIPS_LO16: usize = 6; +pub const R_MIPS_GPREL16: usize = 7; +pub const R_MIPS_LITERAL: usize = 8; +pub const R_MIPS_GOT16: usize = 9; +pub const R_MIPS_PC16: usize = 10; +pub const R_MIPS_CALL16: usize = 11; +pub const R_MIPS_GPREL32: usize = 12; +pub const R_MIPS_SHIFT5: usize = 16; +pub const R_MIPS_SHIFT6: usize = 17; +pub const R_MIPS_64: usize = 18; +pub const R_MIPS_GOT_DISP: usize = 19; +pub const R_MIPS_GOT_PAGE: usize = 20; +pub const R_MIPS_GOT_OFST: usize = 21; +pub const R_MIPS_GOT_HI16: usize = 22; +pub const R_MIPS_GOT_LO16: usize = 23; +pub const R_MIPS_SUB: usize = 24; +pub const R_MIPS_INSERT_A: usize = 25; +pub const R_MIPS_INSERT_B: usize = 26; +pub const R_MIPS_DELETE: usize = 27; +pub const R_MIPS_HIGHER: usize = 28; +pub const R_MIPS_HIGHEST: usize = 29; +pub const R_MIPS_CALL_HI16: usize = 30; +pub const R_MIPS_CALL_LO16: usize = 31; +pub const R_MIPS_SCN_DISP: usize = 32; +pub const R_MIPS_REL16: usize = 33; +pub const R_MIPS_ADD_IMMEDIATE: usize = 34; +pub const R_MIPS_PJUMP: usize = 35; +pub const R_MIPS_RELGOT: usize = 36; +pub const R_MIPS_JALR: usize = 37; +pub const R_MIPS_TLS_DTPMOD32: usize = 38; +pub const R_MIPS_TLS_DTPREL32: usize = 39; +pub const R_MIPS_TLS_DTPMOD64: usize = 40; +pub const R_MIPS_TLS_DTPREL64: usize = 41; +pub const R_MIPS_TLS_GD: usize = 42; +pub const R_MIPS_TLS_LDM: usize = 43; +pub const R_MIPS_TLS_DTPREL_HI16: usize = 44; +pub const R_MIPS_TLS_DTPREL_LO16: usize = 45; +pub const R_MIPS_TLS_GOTTPREL: usize = 46; +pub const R_MIPS_TLS_TPREL32: usize = 47; +pub const R_MIPS_TLS_TPREL64: usize = 48; +pub const R_MIPS_TLS_TPREL_HI16: usize = 49; +pub const R_MIPS_TLS_TPREL_LO16: usize = 50; +pub const R_MIPS_GLOB_DAT: usize = 51; +pub const R_MIPS_COPY: usize = 126; +pub const R_MIPS_JUMP_SLOT: usize = 127; +pub const R_MIPS_NUM: usize = 128; +pub const PT_MIPS_REGINFO: usize = 1879048192; +pub const PT_MIPS_RTPROC: usize = 1879048193; +pub const PT_MIPS_OPTIONS: usize = 1879048194; +pub const PF_MIPS_LOCAL: usize = 268435456; +pub const DT_MIPS_RLD_VERSION: usize = 1879048193; +pub const DT_MIPS_TIME_STAMP: usize = 1879048194; +pub const DT_MIPS_ICHECKSUM: usize = 1879048195; +pub const DT_MIPS_IVERSION: usize = 1879048196; +pub const DT_MIPS_FLAGS: usize = 1879048197; +pub const DT_MIPS_BASE_ADDRESS: usize = 1879048198; +pub const DT_MIPS_MSYM: usize = 1879048199; +pub const DT_MIPS_CONFLICT: usize = 1879048200; +pub const DT_MIPS_LIBLIST: usize = 1879048201; +pub const DT_MIPS_LOCAL_GOTNO: usize = 1879048202; +pub const DT_MIPS_CONFLICTNO: usize = 1879048203; +pub const DT_MIPS_LIBLISTNO: usize = 1879048208; +pub const DT_MIPS_SYMTABNO: usize = 1879048209; +pub const DT_MIPS_UNREFEXTNO: usize = 1879048210; +pub const DT_MIPS_GOTSYM: usize = 1879048211; +pub const DT_MIPS_HIPAGENO: usize = 1879048212; +pub const DT_MIPS_RLD_MAP: usize = 1879048214; +pub const DT_MIPS_DELTA_CLASS: usize = 1879048215; +pub const DT_MIPS_DELTA_CLASS_NO: usize = 1879048216; +pub const DT_MIPS_DELTA_INSTANCE: usize = 1879048217; +pub const DT_MIPS_DELTA_INSTANCE_NO: usize = 1879048218; +pub const DT_MIPS_DELTA_RELOC: usize = 1879048219; +pub const DT_MIPS_DELTA_RELOC_NO: usize = 1879048220; +pub const DT_MIPS_DELTA_SYM: usize = 1879048221; +pub const DT_MIPS_DELTA_SYM_NO: usize = 1879048222; +pub const DT_MIPS_DELTA_CLASSSYM: usize = 1879048224; +pub const DT_MIPS_DELTA_CLASSSYM_NO: usize = 1879048225; +pub const DT_MIPS_CXX_FLAGS: usize = 1879048226; +pub const DT_MIPS_PIXIE_INIT: usize = 1879048227; +pub const DT_MIPS_SYMBOL_LIB: usize = 1879048228; +pub const DT_MIPS_LOCALPAGE_GOTIDX: usize = 1879048229; +pub const DT_MIPS_LOCAL_GOTIDX: usize = 1879048230; +pub const DT_MIPS_HIDDEN_GOTIDX: usize = 1879048231; +pub const DT_MIPS_PROTECTED_GOTIDX: usize = 1879048232; +pub const DT_MIPS_OPTIONS: usize = 1879048233; +pub const DT_MIPS_INTERFACE: usize = 1879048234; +pub const DT_MIPS_DYNSTR_ALIGN: usize = 1879048235; +pub const DT_MIPS_INTERFACE_SIZE: usize = 1879048236; +pub const DT_MIPS_RLD_TEXT_RESOLVE_ADDR: usize = 1879048237; +pub const DT_MIPS_PERF_SUFFIX: usize = 1879048238; +pub const DT_MIPS_COMPACT_SIZE: usize = 1879048239; +pub const DT_MIPS_GP_VALUE: usize = 1879048240; +pub const DT_MIPS_AUX_DYNAMIC: usize = 1879048241; +pub const DT_MIPS_PLTGOT: usize = 1879048242; +pub const DT_MIPS_RWPLT: usize = 1879048244; +pub const DT_MIPS_NUM: usize = 53; +pub const RHF_NONE: usize = 0; +pub const RHF_QUICKSTART: usize = 1; +pub const RHF_NOTPOT: usize = 2; +pub const RHF_NO_LIBRARY_REPLACEMENT: usize = 4; +pub const RHF_NO_MOVE: usize = 8; +pub const RHF_SGI_ONLY: usize = 16; +pub const RHF_GUARANTEE_INIT: usize = 32; +pub const RHF_DELTA_C_PLUS_PLUS: usize = 64; +pub const RHF_GUARANTEE_START_INIT: usize = 128; +pub const RHF_PIXIE: usize = 256; +pub const RHF_DEFAULT_DELAY_LOAD: usize = 512; +pub const RHF_REQUICKSTART: usize = 1024; +pub const RHF_REQUICKSTARTED: usize = 2048; +pub const RHF_CORD: usize = 4096; +pub const RHF_NO_UNRES_UNDEF: usize = 8192; +pub const RHF_RLD_ORDER_SAFE: usize = 16384; +pub const LL_NONE: usize = 0; +pub const LL_EXACT_MATCH: usize = 1; +pub const LL_IGNORE_INT_VER: usize = 2; +pub const LL_REQUIRE_MINOR: usize = 4; +pub const LL_EXPORTS: usize = 8; +pub const LL_DELAY_LOAD: usize = 16; +pub const LL_DELTA: usize = 32; +pub const EF_PARISC_TRAPNIL: usize = 65536; +pub const EF_PARISC_EXT: usize = 131072; +pub const EF_PARISC_LSB: usize = 262144; +pub const EF_PARISC_WIDE: usize = 524288; +pub const EF_PARISC_NO_KABP: usize = 1048576; +pub const EF_PARISC_LAZYSWAP: usize = 4194304; +pub const EF_PARISC_ARCH: usize = 65535; +pub const EFA_PARISC_1_0: usize = 523; +pub const EFA_PARISC_1_1: usize = 528; +pub const EFA_PARISC_2_0: usize = 532; +pub const SHN_PARISC_ANSI_COMMON: usize = 65280; +pub const SHN_PARISC_HUGE_COMMON: usize = 65281; +pub const SHT_PARISC_EXT: usize = 1879048192; +pub const SHT_PARISC_UNWIND: usize = 1879048193; +pub const SHT_PARISC_DOC: usize = 1879048194; +pub const SHF_PARISC_SHORT: usize = 536870912; +pub const SHF_PARISC_HUGE: usize = 1073741824; +pub const SHF_PARISC_SBP: usize = 2147483648; +pub const STT_PARISC_MILLICODE: usize = 13; +pub const STT_HP_OPAQUE: usize = 11; +pub const STT_HP_STUB: usize = 12; +pub const R_PARISC_NONE: usize = 0; +pub const R_PARISC_DIR32: usize = 1; +pub const R_PARISC_DIR21L: usize = 2; +pub const R_PARISC_DIR17R: usize = 3; +pub const R_PARISC_DIR17F: usize = 4; +pub const R_PARISC_DIR14R: usize = 6; +pub const R_PARISC_PCREL32: usize = 9; +pub const R_PARISC_PCREL21L: usize = 10; +pub const R_PARISC_PCREL17R: usize = 11; +pub const R_PARISC_PCREL17F: usize = 12; +pub const R_PARISC_PCREL14R: usize = 14; +pub const R_PARISC_DPREL21L: usize = 18; +pub const R_PARISC_DPREL14R: usize = 22; +pub const R_PARISC_GPREL21L: usize = 26; +pub const R_PARISC_GPREL14R: usize = 30; +pub const R_PARISC_LTOFF21L: usize = 34; +pub const R_PARISC_LTOFF14R: usize = 38; +pub const R_PARISC_SECREL32: usize = 41; +pub const R_PARISC_SEGBASE: usize = 48; +pub const R_PARISC_SEGREL32: usize = 49; +pub const R_PARISC_PLTOFF21L: usize = 50; +pub const R_PARISC_PLTOFF14R: usize = 54; +pub const R_PARISC_LTOFF_FPTR32: usize = 57; +pub const R_PARISC_LTOFF_FPTR21L: usize = 58; +pub const R_PARISC_LTOFF_FPTR14R: usize = 62; +pub const R_PARISC_FPTR64: usize = 64; +pub const R_PARISC_PLABEL32: usize = 65; +pub const R_PARISC_PLABEL21L: usize = 66; +pub const R_PARISC_PLABEL14R: usize = 70; +pub const R_PARISC_PCREL64: usize = 72; +pub const R_PARISC_PCREL22F: usize = 74; +pub const R_PARISC_PCREL14WR: usize = 75; +pub const R_PARISC_PCREL14DR: usize = 76; +pub const R_PARISC_PCREL16F: usize = 77; +pub const R_PARISC_PCREL16WF: usize = 78; +pub const R_PARISC_PCREL16DF: usize = 79; +pub const R_PARISC_DIR64: usize = 80; +pub const R_PARISC_DIR14WR: usize = 83; +pub const R_PARISC_DIR14DR: usize = 84; +pub const R_PARISC_DIR16F: usize = 85; +pub const R_PARISC_DIR16WF: usize = 86; +pub const R_PARISC_DIR16DF: usize = 87; +pub const R_PARISC_GPREL64: usize = 88; +pub const R_PARISC_GPREL14WR: usize = 91; +pub const R_PARISC_GPREL14DR: usize = 92; +pub const R_PARISC_GPREL16F: usize = 93; +pub const R_PARISC_GPREL16WF: usize = 94; +pub const R_PARISC_GPREL16DF: usize = 95; +pub const R_PARISC_LTOFF64: usize = 96; +pub const R_PARISC_LTOFF14WR: usize = 99; +pub const R_PARISC_LTOFF14DR: usize = 100; +pub const R_PARISC_LTOFF16F: usize = 101; +pub const R_PARISC_LTOFF16WF: usize = 102; +pub const R_PARISC_LTOFF16DF: usize = 103; +pub const R_PARISC_SECREL64: usize = 104; +pub const R_PARISC_SEGREL64: usize = 112; +pub const R_PARISC_PLTOFF14WR: usize = 115; +pub const R_PARISC_PLTOFF14DR: usize = 116; +pub const R_PARISC_PLTOFF16F: usize = 117; +pub const R_PARISC_PLTOFF16WF: usize = 118; +pub const R_PARISC_PLTOFF16DF: usize = 119; +pub const R_PARISC_LTOFF_FPTR64: usize = 120; +pub const R_PARISC_LTOFF_FPTR14WR: usize = 123; +pub const R_PARISC_LTOFF_FPTR14DR: usize = 124; +pub const R_PARISC_LTOFF_FPTR16F: usize = 125; +pub const R_PARISC_LTOFF_FPTR16WF: usize = 126; +pub const R_PARISC_LTOFF_FPTR16DF: usize = 127; +pub const R_PARISC_LORESERVE: usize = 128; +pub const R_PARISC_COPY: usize = 128; +pub const R_PARISC_IPLT: usize = 129; +pub const R_PARISC_EPLT: usize = 130; +pub const R_PARISC_TPREL32: usize = 153; +pub const R_PARISC_TPREL21L: usize = 154; +pub const R_PARISC_TPREL14R: usize = 158; +pub const R_PARISC_LTOFF_TP21L: usize = 162; +pub const R_PARISC_LTOFF_TP14R: usize = 166; +pub const R_PARISC_LTOFF_TP14F: usize = 167; +pub const R_PARISC_TPREL64: usize = 216; +pub const R_PARISC_TPREL14WR: usize = 219; +pub const R_PARISC_TPREL14DR: usize = 220; +pub const R_PARISC_TPREL16F: usize = 221; +pub const R_PARISC_TPREL16WF: usize = 222; +pub const R_PARISC_TPREL16DF: usize = 223; +pub const R_PARISC_LTOFF_TP64: usize = 224; +pub const R_PARISC_LTOFF_TP14WR: usize = 227; +pub const R_PARISC_LTOFF_TP14DR: usize = 228; +pub const R_PARISC_LTOFF_TP16F: usize = 229; +pub const R_PARISC_LTOFF_TP16WF: usize = 230; +pub const R_PARISC_LTOFF_TP16DF: usize = 231; +pub const R_PARISC_GNU_VTENTRY: usize = 232; +pub const R_PARISC_GNU_VTINHERIT: usize = 233; +pub const R_PARISC_TLS_GD21L: usize = 234; +pub const R_PARISC_TLS_GD14R: usize = 235; +pub const R_PARISC_TLS_GDCALL: usize = 236; +pub const R_PARISC_TLS_LDM21L: usize = 237; +pub const R_PARISC_TLS_LDM14R: usize = 238; +pub const R_PARISC_TLS_LDMCALL: usize = 239; +pub const R_PARISC_TLS_LDO21L: usize = 240; +pub const R_PARISC_TLS_LDO14R: usize = 241; +pub const R_PARISC_TLS_DTPMOD32: usize = 242; +pub const R_PARISC_TLS_DTPMOD64: usize = 243; +pub const R_PARISC_TLS_DTPOFF32: usize = 244; +pub const R_PARISC_TLS_DTPOFF64: usize = 245; +pub const R_PARISC_TLS_LE21L: usize = 154; +pub const R_PARISC_TLS_LE14R: usize = 158; +pub const R_PARISC_TLS_IE21L: usize = 162; +pub const R_PARISC_TLS_IE14R: usize = 166; +pub const R_PARISC_TLS_TPREL32: usize = 153; +pub const R_PARISC_TLS_TPREL64: usize = 216; +pub const R_PARISC_HIRESERVE: usize = 255; +pub const PT_HP_TLS: usize = 1610612736; +pub const PT_HP_CORE_NONE: usize = 1610612737; +pub const PT_HP_CORE_VERSION: usize = 1610612738; +pub const PT_HP_CORE_KERNEL: usize = 1610612739; +pub const PT_HP_CORE_COMM: usize = 1610612740; +pub const PT_HP_CORE_PROC: usize = 1610612741; +pub const PT_HP_CORE_LOADABLE: usize = 1610612742; +pub const PT_HP_CORE_STACK: usize = 1610612743; +pub const PT_HP_CORE_SHM: usize = 1610612744; +pub const PT_HP_CORE_MMF: usize = 1610612745; +pub const PT_HP_PARALLEL: usize = 1610612752; +pub const PT_HP_FASTBIND: usize = 1610612753; +pub const PT_HP_OPT_ANNOT: usize = 1610612754; +pub const PT_HP_HSL_ANNOT: usize = 1610612755; +pub const PT_HP_STACK: usize = 1610612756; +pub const PT_PARISC_ARCHEXT: usize = 1879048192; +pub const PT_PARISC_UNWIND: usize = 1879048193; +pub const PF_PARISC_SBP: usize = 134217728; +pub const PF_HP_PAGE_SIZE: usize = 1048576; +pub const PF_HP_FAR_SHARED: usize = 2097152; +pub const PF_HP_NEAR_SHARED: usize = 4194304; +pub const PF_HP_CODE: usize = 16777216; +pub const PF_HP_MODIFY: usize = 33554432; +pub const PF_HP_LAZYSWAP: usize = 67108864; +pub const PF_HP_SBP: usize = 134217728; +pub const EF_ALPHA_32BIT: usize = 1; +pub const EF_ALPHA_CANRELAX: usize = 2; +pub const SHT_ALPHA_DEBUG: usize = 1879048193; +pub const SHT_ALPHA_REGINFO: usize = 1879048194; +pub const SHF_ALPHA_GPREL: usize = 268435456; +pub const STO_ALPHA_NOPV: usize = 128; +pub const STO_ALPHA_STD_GPLOAD: usize = 136; +pub const R_ALPHA_NONE: usize = 0; +pub const R_ALPHA_REFLONG: usize = 1; +pub const R_ALPHA_REFQUAD: usize = 2; +pub const R_ALPHA_GPREL32: usize = 3; +pub const R_ALPHA_LITERAL: usize = 4; +pub const R_ALPHA_LITUSE: usize = 5; +pub const R_ALPHA_GPDISP: usize = 6; +pub const R_ALPHA_BRADDR: usize = 7; +pub const R_ALPHA_HINT: usize = 8; +pub const R_ALPHA_SREL16: usize = 9; +pub const R_ALPHA_SREL32: usize = 10; +pub const R_ALPHA_SREL64: usize = 11; +pub const R_ALPHA_GPRELHIGH: usize = 17; +pub const R_ALPHA_GPRELLOW: usize = 18; +pub const R_ALPHA_GPREL16: usize = 19; +pub const R_ALPHA_COPY: usize = 24; +pub const R_ALPHA_GLOB_DAT: usize = 25; +pub const R_ALPHA_JMP_SLOT: usize = 26; +pub const R_ALPHA_RELATIVE: usize = 27; +pub const R_ALPHA_TLS_GD_HI: usize = 28; +pub const R_ALPHA_TLSGD: usize = 29; +pub const R_ALPHA_TLS_LDM: usize = 30; +pub const R_ALPHA_DTPMOD64: usize = 31; +pub const R_ALPHA_GOTDTPREL: usize = 32; +pub const R_ALPHA_DTPREL64: usize = 33; +pub const R_ALPHA_DTPRELHI: usize = 34; +pub const R_ALPHA_DTPRELLO: usize = 35; +pub const R_ALPHA_DTPREL16: usize = 36; +pub const R_ALPHA_GOTTPREL: usize = 37; +pub const R_ALPHA_TPREL64: usize = 38; +pub const R_ALPHA_TPRELHI: usize = 39; +pub const R_ALPHA_TPRELLO: usize = 40; +pub const R_ALPHA_TPREL16: usize = 41; +pub const R_ALPHA_NUM: usize = 46; +pub const LITUSE_ALPHA_ADDR: usize = 0; +pub const LITUSE_ALPHA_BASE: usize = 1; +pub const LITUSE_ALPHA_BYTOFF: usize = 2; +pub const LITUSE_ALPHA_JSR: usize = 3; +pub const LITUSE_ALPHA_TLS_GD: usize = 4; +pub const LITUSE_ALPHA_TLS_LDM: usize = 5; +pub const DT_ALPHA_PLTRO: usize = 1879048192; +pub const DT_ALPHA_NUM: usize = 1; +pub const EF_PPC_EMB: usize = 2147483648; +pub const EF_PPC_RELOCATABLE: usize = 65536; +pub const EF_PPC_RELOCATABLE_LIB: usize = 32768; +pub const R_PPC_NONE: usize = 0; +pub const R_PPC_ADDR32: usize = 1; +pub const R_PPC_ADDR24: usize = 2; +pub const R_PPC_ADDR16: usize = 3; +pub const R_PPC_ADDR16_LO: usize = 4; +pub const R_PPC_ADDR16_HI: usize = 5; +pub const R_PPC_ADDR16_HA: usize = 6; +pub const R_PPC_ADDR14: usize = 7; +pub const R_PPC_ADDR14_BRTAKEN: usize = 8; +pub const R_PPC_ADDR14_BRNTAKEN: usize = 9; +pub const R_PPC_REL24: usize = 10; +pub const R_PPC_REL14: usize = 11; +pub const R_PPC_REL14_BRTAKEN: usize = 12; +pub const R_PPC_REL14_BRNTAKEN: usize = 13; +pub const R_PPC_GOT16: usize = 14; +pub const R_PPC_GOT16_LO: usize = 15; +pub const R_PPC_GOT16_HI: usize = 16; +pub const R_PPC_GOT16_HA: usize = 17; +pub const R_PPC_PLTREL24: usize = 18; +pub const R_PPC_COPY: usize = 19; +pub const R_PPC_GLOB_DAT: usize = 20; +pub const R_PPC_JMP_SLOT: usize = 21; +pub const R_PPC_RELATIVE: usize = 22; +pub const R_PPC_LOCAL24PC: usize = 23; +pub const R_PPC_UADDR32: usize = 24; +pub const R_PPC_UADDR16: usize = 25; +pub const R_PPC_REL32: usize = 26; +pub const R_PPC_PLT32: usize = 27; +pub const R_PPC_PLTREL32: usize = 28; +pub const R_PPC_PLT16_LO: usize = 29; +pub const R_PPC_PLT16_HI: usize = 30; +pub const R_PPC_PLT16_HA: usize = 31; +pub const R_PPC_SDAREL16: usize = 32; +pub const R_PPC_SECTOFF: usize = 33; +pub const R_PPC_SECTOFF_LO: usize = 34; +pub const R_PPC_SECTOFF_HI: usize = 35; +pub const R_PPC_SECTOFF_HA: usize = 36; +pub const R_PPC_TLS: usize = 67; +pub const R_PPC_DTPMOD32: usize = 68; +pub const R_PPC_TPREL16: usize = 69; +pub const R_PPC_TPREL16_LO: usize = 70; +pub const R_PPC_TPREL16_HI: usize = 71; +pub const R_PPC_TPREL16_HA: usize = 72; +pub const R_PPC_TPREL32: usize = 73; +pub const R_PPC_DTPREL16: usize = 74; +pub const R_PPC_DTPREL16_LO: usize = 75; +pub const R_PPC_DTPREL16_HI: usize = 76; +pub const R_PPC_DTPREL16_HA: usize = 77; +pub const R_PPC_DTPREL32: usize = 78; +pub const R_PPC_GOT_TLSGD16: usize = 79; +pub const R_PPC_GOT_TLSGD16_LO: usize = 80; +pub const R_PPC_GOT_TLSGD16_HI: usize = 81; +pub const R_PPC_GOT_TLSGD16_HA: usize = 82; +pub const R_PPC_GOT_TLSLD16: usize = 83; +pub const R_PPC_GOT_TLSLD16_LO: usize = 84; +pub const R_PPC_GOT_TLSLD16_HI: usize = 85; +pub const R_PPC_GOT_TLSLD16_HA: usize = 86; +pub const R_PPC_GOT_TPREL16: usize = 87; +pub const R_PPC_GOT_TPREL16_LO: usize = 88; +pub const R_PPC_GOT_TPREL16_HI: usize = 89; +pub const R_PPC_GOT_TPREL16_HA: usize = 90; +pub const R_PPC_GOT_DTPREL16: usize = 91; +pub const R_PPC_GOT_DTPREL16_LO: usize = 92; +pub const R_PPC_GOT_DTPREL16_HI: usize = 93; +pub const R_PPC_GOT_DTPREL16_HA: usize = 94; +pub const R_PPC_EMB_NADDR32: usize = 101; +pub const R_PPC_EMB_NADDR16: usize = 102; +pub const R_PPC_EMB_NADDR16_LO: usize = 103; +pub const R_PPC_EMB_NADDR16_HI: usize = 104; +pub const R_PPC_EMB_NADDR16_HA: usize = 105; +pub const R_PPC_EMB_SDAI16: usize = 106; +pub const R_PPC_EMB_SDA2I16: usize = 107; +pub const R_PPC_EMB_SDA2REL: usize = 108; +pub const R_PPC_EMB_SDA21: usize = 109; +pub const R_PPC_EMB_MRKREF: usize = 110; +pub const R_PPC_EMB_RELSEC16: usize = 111; +pub const R_PPC_EMB_RELST_LO: usize = 112; +pub const R_PPC_EMB_RELST_HI: usize = 113; +pub const R_PPC_EMB_RELST_HA: usize = 114; +pub const R_PPC_EMB_BIT_FLD: usize = 115; +pub const R_PPC_EMB_RELSDA: usize = 116; +pub const R_PPC_DIAB_SDA21_LO: usize = 180; +pub const R_PPC_DIAB_SDA21_HI: usize = 181; +pub const R_PPC_DIAB_SDA21_HA: usize = 182; +pub const R_PPC_DIAB_RELSDA_LO: usize = 183; +pub const R_PPC_DIAB_RELSDA_HI: usize = 184; +pub const R_PPC_DIAB_RELSDA_HA: usize = 185; +pub const R_PPC_IRELATIVE: usize = 248; +pub const R_PPC_REL16: usize = 249; +pub const R_PPC_REL16_LO: usize = 250; +pub const R_PPC_REL16_HI: usize = 251; +pub const R_PPC_REL16_HA: usize = 252; +pub const R_PPC_TOC16: usize = 255; +pub const DT_PPC_GOT: usize = 1879048192; +pub const DT_PPC_NUM: usize = 1; +pub const R_PPC64_NONE: usize = 0; +pub const R_PPC64_ADDR32: usize = 1; +pub const R_PPC64_ADDR24: usize = 2; +pub const R_PPC64_ADDR16: usize = 3; +pub const R_PPC64_ADDR16_LO: usize = 4; +pub const R_PPC64_ADDR16_HI: usize = 5; +pub const R_PPC64_ADDR16_HA: usize = 6; +pub const R_PPC64_ADDR14: usize = 7; +pub const R_PPC64_ADDR14_BRTAKEN: usize = 8; +pub const R_PPC64_ADDR14_BRNTAKEN: usize = 9; +pub const R_PPC64_REL24: usize = 10; +pub const R_PPC64_REL14: usize = 11; +pub const R_PPC64_REL14_BRTAKEN: usize = 12; +pub const R_PPC64_REL14_BRNTAKEN: usize = 13; +pub const R_PPC64_GOT16: usize = 14; +pub const R_PPC64_GOT16_LO: usize = 15; +pub const R_PPC64_GOT16_HI: usize = 16; +pub const R_PPC64_GOT16_HA: usize = 17; +pub const R_PPC64_COPY: usize = 19; +pub const R_PPC64_GLOB_DAT: usize = 20; +pub const R_PPC64_JMP_SLOT: usize = 21; +pub const R_PPC64_RELATIVE: usize = 22; +pub const R_PPC64_UADDR32: usize = 24; +pub const R_PPC64_UADDR16: usize = 25; +pub const R_PPC64_REL32: usize = 26; +pub const R_PPC64_PLT32: usize = 27; +pub const R_PPC64_PLTREL32: usize = 28; +pub const R_PPC64_PLT16_LO: usize = 29; +pub const R_PPC64_PLT16_HI: usize = 30; +pub const R_PPC64_PLT16_HA: usize = 31; +pub const R_PPC64_SECTOFF: usize = 33; +pub const R_PPC64_SECTOFF_LO: usize = 34; +pub const R_PPC64_SECTOFF_HI: usize = 35; +pub const R_PPC64_SECTOFF_HA: usize = 36; +pub const R_PPC64_ADDR30: usize = 37; +pub const R_PPC64_ADDR64: usize = 38; +pub const R_PPC64_ADDR16_HIGHER: usize = 39; +pub const R_PPC64_ADDR16_HIGHERA: usize = 40; +pub const R_PPC64_ADDR16_HIGHEST: usize = 41; +pub const R_PPC64_ADDR16_HIGHESTA: usize = 42; +pub const R_PPC64_UADDR64: usize = 43; +pub const R_PPC64_REL64: usize = 44; +pub const R_PPC64_PLT64: usize = 45; +pub const R_PPC64_PLTREL64: usize = 46; +pub const R_PPC64_TOC16: usize = 47; +pub const R_PPC64_TOC16_LO: usize = 48; +pub const R_PPC64_TOC16_HI: usize = 49; +pub const R_PPC64_TOC16_HA: usize = 50; +pub const R_PPC64_TOC: usize = 51; +pub const R_PPC64_PLTGOT16: usize = 52; +pub const R_PPC64_PLTGOT16_LO: usize = 53; +pub const R_PPC64_PLTGOT16_HI: usize = 54; +pub const R_PPC64_PLTGOT16_HA: usize = 55; +pub const R_PPC64_ADDR16_DS: usize = 56; +pub const R_PPC64_ADDR16_LO_DS: usize = 57; +pub const R_PPC64_GOT16_DS: usize = 58; +pub const R_PPC64_GOT16_LO_DS: usize = 59; +pub const R_PPC64_PLT16_LO_DS: usize = 60; +pub const R_PPC64_SECTOFF_DS: usize = 61; +pub const R_PPC64_SECTOFF_LO_DS: usize = 62; +pub const R_PPC64_TOC16_DS: usize = 63; +pub const R_PPC64_TOC16_LO_DS: usize = 64; +pub const R_PPC64_PLTGOT16_DS: usize = 65; +pub const R_PPC64_PLTGOT16_LO_DS: usize = 66; +pub const R_PPC64_TLS: usize = 67; +pub const R_PPC64_DTPMOD64: usize = 68; +pub const R_PPC64_TPREL16: usize = 69; +pub const R_PPC64_TPREL16_LO: usize = 70; +pub const R_PPC64_TPREL16_HI: usize = 71; +pub const R_PPC64_TPREL16_HA: usize = 72; +pub const R_PPC64_TPREL64: usize = 73; +pub const R_PPC64_DTPREL16: usize = 74; +pub const R_PPC64_DTPREL16_LO: usize = 75; +pub const R_PPC64_DTPREL16_HI: usize = 76; +pub const R_PPC64_DTPREL16_HA: usize = 77; +pub const R_PPC64_DTPREL64: usize = 78; +pub const R_PPC64_GOT_TLSGD16: usize = 79; +pub const R_PPC64_GOT_TLSGD16_LO: usize = 80; +pub const R_PPC64_GOT_TLSGD16_HI: usize = 81; +pub const R_PPC64_GOT_TLSGD16_HA: usize = 82; +pub const R_PPC64_GOT_TLSLD16: usize = 83; +pub const R_PPC64_GOT_TLSLD16_LO: usize = 84; +pub const R_PPC64_GOT_TLSLD16_HI: usize = 85; +pub const R_PPC64_GOT_TLSLD16_HA: usize = 86; +pub const R_PPC64_GOT_TPREL16_DS: usize = 87; +pub const R_PPC64_GOT_TPREL16_LO_DS: usize = 88; +pub const R_PPC64_GOT_TPREL16_HI: usize = 89; +pub const R_PPC64_GOT_TPREL16_HA: usize = 90; +pub const R_PPC64_GOT_DTPREL16_DS: usize = 91; +pub const R_PPC64_GOT_DTPREL16_LO_DS: usize = 92; +pub const R_PPC64_GOT_DTPREL16_HI: usize = 93; +pub const R_PPC64_GOT_DTPREL16_HA: usize = 94; +pub const R_PPC64_TPREL16_DS: usize = 95; +pub const R_PPC64_TPREL16_LO_DS: usize = 96; +pub const R_PPC64_TPREL16_HIGHER: usize = 97; +pub const R_PPC64_TPREL16_HIGHERA: usize = 98; +pub const R_PPC64_TPREL16_HIGHEST: usize = 99; +pub const R_PPC64_TPREL16_HIGHESTA: usize = 100; +pub const R_PPC64_DTPREL16_DS: usize = 101; +pub const R_PPC64_DTPREL16_LO_DS: usize = 102; +pub const R_PPC64_DTPREL16_HIGHER: usize = 103; +pub const R_PPC64_DTPREL16_HIGHERA: usize = 104; +pub const R_PPC64_DTPREL16_HIGHEST: usize = 105; +pub const R_PPC64_DTPREL16_HIGHESTA: usize = 106; +pub const R_PPC64_TLSGD: usize = 107; +pub const R_PPC64_TLSLD: usize = 108; +pub const R_PPC64_TOCSAVE: usize = 109; +pub const R_PPC64_ADDR16_HIGH: usize = 110; +pub const R_PPC64_ADDR16_HIGHA: usize = 111; +pub const R_PPC64_TPREL16_HIGH: usize = 112; +pub const R_PPC64_TPREL16_HIGHA: usize = 113; +pub const R_PPC64_DTPREL16_HIGH: usize = 114; +pub const R_PPC64_DTPREL16_HIGHA: usize = 115; +pub const R_PPC64_JMP_IREL: usize = 247; +pub const R_PPC64_IRELATIVE: usize = 248; +pub const R_PPC64_REL16: usize = 249; +pub const R_PPC64_REL16_LO: usize = 250; +pub const R_PPC64_REL16_HI: usize = 251; +pub const R_PPC64_REL16_HA: usize = 252; +pub const EF_PPC64_ABI: usize = 3; +pub const DT_PPC64_GLINK: usize = 1879048192; +pub const DT_PPC64_OPD: usize = 1879048193; +pub const DT_PPC64_OPDSZ: usize = 1879048194; +pub const DT_PPC64_OPT: usize = 1879048195; +pub const DT_PPC64_NUM: usize = 3; +pub const PPC64_OPT_TLS: usize = 1; +pub const PPC64_OPT_MULTI_TOC: usize = 2; +pub const STO_PPC64_LOCAL_BIT: usize = 5; +pub const STO_PPC64_LOCAL_MASK: usize = 224; +pub const EF_ARM_RELEXEC: usize = 1; +pub const EF_ARM_HASENTRY: usize = 2; +pub const EF_ARM_INTERWORK: usize = 4; +pub const EF_ARM_APCS_26: usize = 8; +pub const EF_ARM_APCS_FLOAT: usize = 16; +pub const EF_ARM_PIC: usize = 32; +pub const EF_ARM_ALIGN8: usize = 64; +pub const EF_ARM_NEW_ABI: usize = 128; +pub const EF_ARM_OLD_ABI: usize = 256; +pub const EF_ARM_SOFT_FLOAT: usize = 512; +pub const EF_ARM_VFP_FLOAT: usize = 1024; +pub const EF_ARM_MAVERICK_FLOAT: usize = 2048; +pub const EF_ARM_ABI_FLOAT_SOFT: usize = 512; +pub const EF_ARM_ABI_FLOAT_HARD: usize = 1024; +pub const EF_ARM_SYMSARESORTED: usize = 4; +pub const EF_ARM_DYNSYMSUSESEGIDX: usize = 8; +pub const EF_ARM_MAPSYMSFIRST: usize = 16; +pub const EF_ARM_BE8: usize = 8388608; +pub const EF_ARM_LE8: usize = 4194304; +pub const EF_ARM_EABI_UNKNOWN: usize = 0; +pub const EF_ARM_EABI_VER1: usize = 16777216; +pub const EF_ARM_EABI_VER2: usize = 33554432; +pub const EF_ARM_EABI_VER3: usize = 50331648; +pub const EF_ARM_EABI_VER4: usize = 67108864; +pub const EF_ARM_EABI_VER5: usize = 83886080; +pub const STT_ARM_TFUNC: usize = 13; +pub const STT_ARM_16BIT: usize = 15; +pub const SHF_ARM_ENTRYSECT: usize = 268435456; +pub const SHF_ARM_COMDEF: usize = 2147483648; +pub const PF_ARM_SB: usize = 268435456; +pub const PF_ARM_PI: usize = 536870912; +pub const PF_ARM_ABS: usize = 1073741824; +pub const PT_ARM_EXIDX: usize = 1879048193; +pub const SHT_ARM_EXIDX: usize = 1879048193; +pub const SHT_ARM_PREEMPTMAP: usize = 1879048194; +pub const SHT_ARM_ATTRIBUTES: usize = 1879048195; +pub const R_AARCH64_NONE: usize = 0; +pub const R_AARCH64_ABS64: usize = 257; +pub const R_AARCH64_ABS32: usize = 258; +pub const R_AARCH64_ABS16: usize = 259; +pub const R_AARCH64_PREL64: usize = 260; +pub const R_AARCH64_PREL32: usize = 261; +pub const R_AARCH64_PREL16: usize = 262; +pub const R_AARCH64_MOVW_UABS_G0: usize = 263; +pub const R_AARCH64_MOVW_UABS_G0_NC: usize = 264; +pub const R_AARCH64_MOVW_UABS_G1: usize = 265; +pub const R_AARCH64_MOVW_UABS_G1_NC: usize = 266; +pub const R_AARCH64_MOVW_UABS_G2: usize = 267; +pub const R_AARCH64_MOVW_UABS_G2_NC: usize = 268; +pub const R_AARCH64_MOVW_UABS_G3: usize = 269; +pub const R_AARCH64_MOVW_SABS_G0: usize = 270; +pub const R_AARCH64_MOVW_SABS_G1: usize = 271; +pub const R_AARCH64_MOVW_SABS_G2: usize = 272; +pub const R_AARCH64_LD_PREL_LO19: usize = 273; +pub const R_AARCH64_ADR_PREL_LO21: usize = 274; +pub const R_AARCH64_ADR_PREL_PG_HI21: usize = 275; +pub const R_AARCH64_ADR_PREL_PG_HI21_NC: usize = 276; +pub const R_AARCH64_ADD_ABS_LO12_NC: usize = 277; +pub const R_AARCH64_LDST8_ABS_LO12_NC: usize = 278; +pub const R_AARCH64_TSTBR14: usize = 279; +pub const R_AARCH64_CONDBR19: usize = 280; +pub const R_AARCH64_JUMP26: usize = 282; +pub const R_AARCH64_CALL26: usize = 283; +pub const R_AARCH64_LDST16_ABS_LO12_NC: usize = 284; +pub const R_AARCH64_LDST32_ABS_LO12_NC: usize = 285; +pub const R_AARCH64_LDST64_ABS_LO12_NC: usize = 286; +pub const R_AARCH64_MOVW_PREL_G0: usize = 287; +pub const R_AARCH64_MOVW_PREL_G0_NC: usize = 288; +pub const R_AARCH64_MOVW_PREL_G1: usize = 289; +pub const R_AARCH64_MOVW_PREL_G1_NC: usize = 290; +pub const R_AARCH64_MOVW_PREL_G2: usize = 291; +pub const R_AARCH64_MOVW_PREL_G2_NC: usize = 292; +pub const R_AARCH64_MOVW_PREL_G3: usize = 293; +pub const R_AARCH64_LDST128_ABS_LO12_NC: usize = 299; +pub const R_AARCH64_MOVW_GOTOFF_G0: usize = 300; +pub const R_AARCH64_MOVW_GOTOFF_G0_NC: usize = 301; +pub const R_AARCH64_MOVW_GOTOFF_G1: usize = 302; +pub const R_AARCH64_MOVW_GOTOFF_G1_NC: usize = 303; +pub const R_AARCH64_MOVW_GOTOFF_G2: usize = 304; +pub const R_AARCH64_MOVW_GOTOFF_G2_NC: usize = 305; +pub const R_AARCH64_MOVW_GOTOFF_G3: usize = 306; +pub const R_AARCH64_GOTREL64: usize = 307; +pub const R_AARCH64_GOTREL32: usize = 308; +pub const R_AARCH64_GOT_LD_PREL19: usize = 309; +pub const R_AARCH64_LD64_GOTOFF_LO15: usize = 310; +pub const R_AARCH64_ADR_GOT_PAGE: usize = 311; +pub const R_AARCH64_LD64_GOT_LO12_NC: usize = 312; +pub const R_AARCH64_LD64_GOTPAGE_LO15: usize = 313; +pub const R_AARCH64_TLSGD_ADR_PREL21: usize = 512; +pub const R_AARCH64_TLSGD_ADR_PAGE21: usize = 513; +pub const R_AARCH64_TLSGD_ADD_LO12_NC: usize = 514; +pub const R_AARCH64_TLSGD_MOVW_G1: usize = 515; +pub const R_AARCH64_TLSGD_MOVW_G0_NC: usize = 516; +pub const R_AARCH64_TLSLD_ADR_PREL21: usize = 517; +pub const R_AARCH64_TLSLD_ADR_PAGE21: usize = 518; +pub const R_AARCH64_TLSLD_ADD_LO12_NC: usize = 519; +pub const R_AARCH64_TLSLD_MOVW_G1: usize = 520; +pub const R_AARCH64_TLSLD_MOVW_G0_NC: usize = 521; +pub const R_AARCH64_TLSLD_LD_PREL19: usize = 522; +pub const R_AARCH64_TLSLD_MOVW_DTPREL_G2: usize = 523; +pub const R_AARCH64_TLSLD_MOVW_DTPREL_G1: usize = 524; +pub const R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC: usize = 525; +pub const R_AARCH64_TLSLD_MOVW_DTPREL_G0: usize = 526; +pub const R_AARCH64_TLSLD_MOVW_DTPREL_G0_NC: usize = 527; +pub const R_AARCH64_TLSLD_ADD_DTPREL_HI12: usize = 528; +pub const R_AARCH64_TLSLD_ADD_DTPREL_LO12: usize = 529; +pub const R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC: usize = 530; +pub const R_AARCH64_TLSLD_LDST8_DTPREL_LO12: usize = 531; +pub const R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC: usize = 532; +pub const R_AARCH64_TLSLD_LDST16_DTPREL_LO12: usize = 533; +pub const R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC: usize = 534; +pub const R_AARCH64_TLSLD_LDST32_DTPREL_LO12: usize = 535; +pub const R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC: usize = 536; +pub const R_AARCH64_TLSLD_LDST64_DTPREL_LO12: usize = 537; +pub const R_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC: usize = 538; +pub const R_AARCH64_TLSIE_MOVW_GOTTPREL_G1: usize = 539; +pub const R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC: usize = 540; +pub const R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21: usize = 541; +pub const R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: usize = 542; +pub const R_AARCH64_TLSIE_LD_GOTTPREL_PREL19: usize = 543; +pub const R_AARCH64_TLSLE_MOVW_TPREL_G2: usize = 544; +pub const R_AARCH64_TLSLE_MOVW_TPREL_G1: usize = 545; +pub const R_AARCH64_TLSLE_MOVW_TPREL_G1_NC: usize = 546; +pub const R_AARCH64_TLSLE_MOVW_TPREL_G0: usize = 547; +pub const R_AARCH64_TLSLE_MOVW_TPREL_G0_NC: usize = 548; +pub const R_AARCH64_TLSLE_ADD_TPREL_HI12: usize = 549; +pub const R_AARCH64_TLSLE_ADD_TPREL_LO12: usize = 550; +pub const R_AARCH64_TLSLE_ADD_TPREL_LO12_NC: usize = 551; +pub const R_AARCH64_TLSLE_LDST8_TPREL_LO12: usize = 552; +pub const R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC: usize = 553; +pub const R_AARCH64_TLSLE_LDST16_TPREL_LO12: usize = 554; +pub const R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC: usize = 555; +pub const R_AARCH64_TLSLE_LDST32_TPREL_LO12: usize = 556; +pub const R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC: usize = 557; +pub const R_AARCH64_TLSLE_LDST64_TPREL_LO12: usize = 558; +pub const R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC: usize = 559; +pub const R_AARCH64_TLSDESC_LD_PREL19: usize = 560; +pub const R_AARCH64_TLSDESC_ADR_PREL21: usize = 561; +pub const R_AARCH64_TLSDESC_ADR_PAGE21: usize = 562; +pub const R_AARCH64_TLSDESC_LD64_LO12: usize = 563; +pub const R_AARCH64_TLSDESC_ADD_LO12: usize = 564; +pub const R_AARCH64_TLSDESC_OFF_G1: usize = 565; +pub const R_AARCH64_TLSDESC_OFF_G0_NC: usize = 566; +pub const R_AARCH64_TLSDESC_LDR: usize = 567; +pub const R_AARCH64_TLSDESC_ADD: usize = 568; +pub const R_AARCH64_TLSDESC_CALL: usize = 569; +pub const R_AARCH64_TLSLE_LDST128_TPREL_LO12: usize = 570; +pub const R_AARCH64_TLSLE_LDST128_TPREL_LO12_NC: usize = 571; +pub const R_AARCH64_TLSLD_LDST128_DTPREL_LO12: usize = 572; +pub const R_AARCH64_TLSLD_LDST128_DTPREL_LO12_NC: usize = + 573; +pub const R_AARCH64_COPY: usize = 1024; +pub const R_AARCH64_GLOB_DAT: usize = 1025; +pub const R_AARCH64_JUMP_SLOT: usize = 1026; +pub const R_AARCH64_RELATIVE: usize = 1027; +pub const R_AARCH64_TLS_DTPMOD64: usize = 1028; +pub const R_AARCH64_TLS_DTPREL64: usize = 1029; +pub const R_AARCH64_TLS_TPREL64: usize = 1030; +pub const R_AARCH64_TLSDESC: usize = 1031; +pub const R_AARCH64_IRELATIVE: usize = 1032; +pub const R_ARM_NONE: usize = 0; +pub const R_ARM_PC24: usize = 1; +pub const R_ARM_ABS32: usize = 2; +pub const R_ARM_REL32: usize = 3; +pub const R_ARM_PC13: usize = 4; +pub const R_ARM_ABS16: usize = 5; +pub const R_ARM_ABS12: usize = 6; +pub const R_ARM_THM_ABS5: usize = 7; +pub const R_ARM_ABS8: usize = 8; +pub const R_ARM_SBREL32: usize = 9; +pub const R_ARM_THM_PC22: usize = 10; +pub const R_ARM_THM_PC8: usize = 11; +pub const R_ARM_AMP_VCALL9: usize = 12; +pub const R_ARM_SWI24: usize = 13; +pub const R_ARM_TLS_DESC: usize = 13; +pub const R_ARM_THM_SWI8: usize = 14; +pub const R_ARM_XPC25: usize = 15; +pub const R_ARM_THM_XPC22: usize = 16; +pub const R_ARM_TLS_DTPMOD32: usize = 17; +pub const R_ARM_TLS_DTPOFF32: usize = 18; +pub const R_ARM_TLS_TPOFF32: usize = 19; +pub const R_ARM_COPY: usize = 20; +pub const R_ARM_GLOB_DAT: usize = 21; +pub const R_ARM_JUMP_SLOT: usize = 22; +pub const R_ARM_RELATIVE: usize = 23; +pub const R_ARM_GOTOFF: usize = 24; +pub const R_ARM_GOTPC: usize = 25; +pub const R_ARM_GOT32: usize = 26; +pub const R_ARM_PLT32: usize = 27; +pub const R_ARM_CALL: usize = 28; +pub const R_ARM_JUMP24: usize = 29; +pub const R_ARM_THM_JUMP24: usize = 30; +pub const R_ARM_BASE_ABS: usize = 31; +pub const R_ARM_ALU_PCREL_7_0: usize = 32; +pub const R_ARM_ALU_PCREL_15_8: usize = 33; +pub const R_ARM_ALU_PCREL_23_15: usize = 34; +pub const R_ARM_LDR_SBREL_11_0: usize = 35; +pub const R_ARM_ALU_SBREL_19_12: usize = 36; +pub const R_ARM_ALU_SBREL_27_20: usize = 37; +pub const R_ARM_TARGET1: usize = 38; +pub const R_ARM_SBREL31: usize = 39; +pub const R_ARM_V4BX: usize = 40; +pub const R_ARM_TARGET2: usize = 41; +pub const R_ARM_PREL31: usize = 42; +pub const R_ARM_MOVW_ABS_NC: usize = 43; +pub const R_ARM_MOVT_ABS: usize = 44; +pub const R_ARM_MOVW_PREL_NC: usize = 45; +pub const R_ARM_MOVT_PREL: usize = 46; +pub const R_ARM_THM_MOVW_ABS_NC: usize = 47; +pub const R_ARM_THM_MOVT_ABS: usize = 48; +pub const R_ARM_THM_MOVW_PREL_NC: usize = 49; +pub const R_ARM_THM_MOVT_PREL: usize = 50; +pub const R_ARM_THM_JUMP19: usize = 51; +pub const R_ARM_THM_JUMP6: usize = 52; +pub const R_ARM_THM_ALU_PREL_11_0: usize = 53; +pub const R_ARM_THM_PC12: usize = 54; +pub const R_ARM_ABS32_NOI: usize = 55; +pub const R_ARM_REL32_NOI: usize = 56; +pub const R_ARM_ALU_PC_G0_NC: usize = 57; +pub const R_ARM_ALU_PC_G0: usize = 58; +pub const R_ARM_ALU_PC_G1_NC: usize = 59; +pub const R_ARM_ALU_PC_G1: usize = 60; +pub const R_ARM_ALU_PC_G2: usize = 61; +pub const R_ARM_LDR_PC_G1: usize = 62; +pub const R_ARM_LDR_PC_G2: usize = 63; +pub const R_ARM_LDRS_PC_G0: usize = 64; +pub const R_ARM_LDRS_PC_G1: usize = 65; +pub const R_ARM_LDRS_PC_G2: usize = 66; +pub const R_ARM_LDC_PC_G0: usize = 67; +pub const R_ARM_LDC_PC_G1: usize = 68; +pub const R_ARM_LDC_PC_G2: usize = 69; +pub const R_ARM_ALU_SB_G0_NC: usize = 70; +pub const R_ARM_ALU_SB_G0: usize = 71; +pub const R_ARM_ALU_SB_G1_NC: usize = 72; +pub const R_ARM_ALU_SB_G1: usize = 73; +pub const R_ARM_ALU_SB_G2: usize = 74; +pub const R_ARM_LDR_SB_G0: usize = 75; +pub const R_ARM_LDR_SB_G1: usize = 76; +pub const R_ARM_LDR_SB_G2: usize = 77; +pub const R_ARM_LDRS_SB_G0: usize = 78; +pub const R_ARM_LDRS_SB_G1: usize = 79; +pub const R_ARM_LDRS_SB_G2: usize = 80; +pub const R_ARM_LDC_SB_G0: usize = 81; +pub const R_ARM_LDC_SB_G1: usize = 82; +pub const R_ARM_LDC_SB_G2: usize = 83; +pub const R_ARM_MOVW_BREL_NC: usize = 84; +pub const R_ARM_MOVT_BREL: usize = 85; +pub const R_ARM_MOVW_BREL: usize = 86; +pub const R_ARM_THM_MOVW_BREL_NC: usize = 87; +pub const R_ARM_THM_MOVT_BREL: usize = 88; +pub const R_ARM_THM_MOVW_BREL: usize = 89; +pub const R_ARM_TLS_GOTDESC: usize = 90; +pub const R_ARM_TLS_CALL: usize = 91; +pub const R_ARM_TLS_DESCSEQ: usize = 92; +pub const R_ARM_THM_TLS_CALL: usize = 93; +pub const R_ARM_PLT32_ABS: usize = 94; +pub const R_ARM_GOT_ABS: usize = 95; +pub const R_ARM_GOT_PREL: usize = 96; +pub const R_ARM_GOT_BREL12: usize = 97; +pub const R_ARM_GOTOFF12: usize = 98; +pub const R_ARM_GOTRELAX: usize = 99; +pub const R_ARM_GNU_VTENTRY: usize = 100; +pub const R_ARM_GNU_VTINHERIT: usize = 101; +pub const R_ARM_THM_PC11: usize = 102; +pub const R_ARM_THM_PC9: usize = 103; +pub const R_ARM_TLS_GD32: usize = 104; +pub const R_ARM_TLS_LDM32: usize = 105; +pub const R_ARM_TLS_LDO32: usize = 106; +pub const R_ARM_TLS_IE32: usize = 107; +pub const R_ARM_TLS_LE32: usize = 108; +pub const R_ARM_TLS_LDO12: usize = 109; +pub const R_ARM_TLS_LE12: usize = 110; +pub const R_ARM_TLS_IE12GP: usize = 111; +pub const R_ARM_ME_TOO: usize = 128; +pub const R_ARM_THM_TLS_DESCSEQ: usize = 129; +pub const R_ARM_THM_TLS_DESCSEQ16: usize = 129; +pub const R_ARM_THM_TLS_DESCSEQ32: usize = 130; +pub const R_ARM_THM_GOT_BREL12: usize = 131; +pub const R_ARM_IRELATIVE: usize = 160; +pub const R_ARM_RXPC25: usize = 249; +pub const R_ARM_RSBREL32: usize = 250; +pub const R_ARM_THM_RPC22: usize = 251; +pub const R_ARM_RREL32: usize = 252; +pub const R_ARM_RABS22: usize = 253; +pub const R_ARM_RPC24: usize = 254; +pub const R_ARM_RBASE: usize = 255; +pub const R_ARM_NUM: usize = 256; +pub const EF_IA_64_MASKOS: usize = 15; +pub const EF_IA_64_ABI64: usize = 16; +pub const EF_IA_64_ARCH: usize = 4278190080; +pub const PT_IA_64_ARCHEXT: usize = 1879048192; +pub const PT_IA_64_UNWIND: usize = 1879048193; +pub const PT_IA_64_HP_OPT_ANOT: usize = 1610612754; +pub const PT_IA_64_HP_HSL_ANOT: usize = 1610612755; +pub const PT_IA_64_HP_STACK: usize = 1610612756; +pub const PF_IA_64_NORECOV: usize = 2147483648; +pub const SHT_IA_64_EXT: usize = 1879048192; +pub const SHT_IA_64_UNWIND: usize = 1879048193; +pub const SHF_IA_64_SHORT: usize = 268435456; +pub const SHF_IA_64_NORECOV: usize = 536870912; +pub const DT_IA_64_PLT_RESERVE: usize = 1879048192; +pub const DT_IA_64_NUM: usize = 1; +pub const R_IA64_NONE: usize = 0; +pub const R_IA64_IMM14: usize = 33; +pub const R_IA64_IMM22: usize = 34; +pub const R_IA64_IMM64: usize = 35; +pub const R_IA64_DIR32MSB: usize = 36; +pub const R_IA64_DIR32LSB: usize = 37; +pub const R_IA64_DIR64MSB: usize = 38; +pub const R_IA64_DIR64LSB: usize = 39; +pub const R_IA64_GPREL22: usize = 42; +pub const R_IA64_GPREL64I: usize = 43; +pub const R_IA64_GPREL32MSB: usize = 44; +pub const R_IA64_GPREL32LSB: usize = 45; +pub const R_IA64_GPREL64MSB: usize = 46; +pub const R_IA64_GPREL64LSB: usize = 47; +pub const R_IA64_LTOFF22: usize = 50; +pub const R_IA64_LTOFF64I: usize = 51; +pub const R_IA64_PLTOFF22: usize = 58; +pub const R_IA64_PLTOFF64I: usize = 59; +pub const R_IA64_PLTOFF64MSB: usize = 62; +pub const R_IA64_PLTOFF64LSB: usize = 63; +pub const R_IA64_FPTR64I: usize = 67; +pub const R_IA64_FPTR32MSB: usize = 68; +pub const R_IA64_FPTR32LSB: usize = 69; +pub const R_IA64_FPTR64MSB: usize = 70; +pub const R_IA64_FPTR64LSB: usize = 71; +pub const R_IA64_PCREL60B: usize = 72; +pub const R_IA64_PCREL21B: usize = 73; +pub const R_IA64_PCREL21M: usize = 74; +pub const R_IA64_PCREL21F: usize = 75; +pub const R_IA64_PCREL32MSB: usize = 76; +pub const R_IA64_PCREL32LSB: usize = 77; +pub const R_IA64_PCREL64MSB: usize = 78; +pub const R_IA64_PCREL64LSB: usize = 79; +pub const R_IA64_LTOFF_FPTR22: usize = 82; +pub const R_IA64_LTOFF_FPTR64I: usize = 83; +pub const R_IA64_LTOFF_FPTR32MSB: usize = 84; +pub const R_IA64_LTOFF_FPTR32LSB: usize = 85; +pub const R_IA64_LTOFF_FPTR64MSB: usize = 86; +pub const R_IA64_LTOFF_FPTR64LSB: usize = 87; +pub const R_IA64_SEGREL32MSB: usize = 92; +pub const R_IA64_SEGREL32LSB: usize = 93; +pub const R_IA64_SEGREL64MSB: usize = 94; +pub const R_IA64_SEGREL64LSB: usize = 95; +pub const R_IA64_SECREL32MSB: usize = 100; +pub const R_IA64_SECREL32LSB: usize = 101; +pub const R_IA64_SECREL64MSB: usize = 102; +pub const R_IA64_SECREL64LSB: usize = 103; +pub const R_IA64_REL32MSB: usize = 108; +pub const R_IA64_REL32LSB: usize = 109; +pub const R_IA64_REL64MSB: usize = 110; +pub const R_IA64_REL64LSB: usize = 111; +pub const R_IA64_LTV32MSB: usize = 116; +pub const R_IA64_LTV32LSB: usize = 117; +pub const R_IA64_LTV64MSB: usize = 118; +pub const R_IA64_LTV64LSB: usize = 119; +pub const R_IA64_PCREL21BI: usize = 121; +pub const R_IA64_PCREL22: usize = 122; +pub const R_IA64_PCREL64I: usize = 123; +pub const R_IA64_IPLTMSB: usize = 128; +pub const R_IA64_IPLTLSB: usize = 129; +pub const R_IA64_COPY: usize = 132; +pub const R_IA64_SUB: usize = 133; +pub const R_IA64_LTOFF22X: usize = 134; +pub const R_IA64_LDXMOV: usize = 135; +pub const R_IA64_TPREL14: usize = 145; +pub const R_IA64_TPREL22: usize = 146; +pub const R_IA64_TPREL64I: usize = 147; +pub const R_IA64_TPREL64MSB: usize = 150; +pub const R_IA64_TPREL64LSB: usize = 151; +pub const R_IA64_LTOFF_TPREL22: usize = 154; +pub const R_IA64_DTPMOD64MSB: usize = 166; +pub const R_IA64_DTPMOD64LSB: usize = 167; +pub const R_IA64_LTOFF_DTPMOD22: usize = 170; +pub const R_IA64_DTPREL14: usize = 177; +pub const R_IA64_DTPREL22: usize = 178; +pub const R_IA64_DTPREL64I: usize = 179; +pub const R_IA64_DTPREL32MSB: usize = 180; +pub const R_IA64_DTPREL32LSB: usize = 181; +pub const R_IA64_DTPREL64MSB: usize = 182; +pub const R_IA64_DTPREL64LSB: usize = 183; +pub const R_IA64_LTOFF_DTPREL22: usize = 186; +pub const EF_SH_MACH_MASK: usize = 31; +pub const EF_SH_UNKNOWN: usize = 0; +pub const EF_SH1: usize = 1; +pub const EF_SH2: usize = 2; +pub const EF_SH3: usize = 3; +pub const EF_SH_DSP: usize = 4; +pub const EF_SH3_DSP: usize = 5; +pub const EF_SH4AL_DSP: usize = 6; +pub const EF_SH3E: usize = 8; +pub const EF_SH4: usize = 9; +pub const EF_SH2E: usize = 11; +pub const EF_SH4A: usize = 12; +pub const EF_SH2A: usize = 13; +pub const EF_SH4_NOFPU: usize = 16; +pub const EF_SH4A_NOFPU: usize = 17; +pub const EF_SH4_NOMMU_NOFPU: usize = 18; +pub const EF_SH2A_NOFPU: usize = 19; +pub const EF_SH3_NOMMU: usize = 20; +pub const EF_SH2A_SH4_NOFPU: usize = 21; +pub const EF_SH2A_SH3_NOFPU: usize = 22; +pub const EF_SH2A_SH4: usize = 23; +pub const EF_SH2A_SH3E: usize = 24; +pub const R_SH_NONE: usize = 0; +pub const R_SH_DIR32: usize = 1; +pub const R_SH_REL32: usize = 2; +pub const R_SH_DIR8WPN: usize = 3; +pub const R_SH_IND12W: usize = 4; +pub const R_SH_DIR8WPL: usize = 5; +pub const R_SH_DIR8WPZ: usize = 6; +pub const R_SH_DIR8BP: usize = 7; +pub const R_SH_DIR8W: usize = 8; +pub const R_SH_DIR8L: usize = 9; +pub const R_SH_SWITCH16: usize = 25; +pub const R_SH_SWITCH32: usize = 26; +pub const R_SH_USES: usize = 27; +pub const R_SH_COUNT: usize = 28; +pub const R_SH_ALIGN: usize = 29; +pub const R_SH_CODE: usize = 30; +pub const R_SH_DATA: usize = 31; +pub const R_SH_LABEL: usize = 32; +pub const R_SH_SWITCH8: usize = 33; +pub const R_SH_GNU_VTINHERIT: usize = 34; +pub const R_SH_GNU_VTENTRY: usize = 35; +pub const R_SH_TLS_GD_32: usize = 144; +pub const R_SH_TLS_LD_32: usize = 145; +pub const R_SH_TLS_LDO_32: usize = 146; +pub const R_SH_TLS_IE_32: usize = 147; +pub const R_SH_TLS_LE_32: usize = 148; +pub const R_SH_TLS_DTPMOD32: usize = 149; +pub const R_SH_TLS_DTPOFF32: usize = 150; +pub const R_SH_TLS_TPOFF32: usize = 151; +pub const R_SH_GOT32: usize = 160; +pub const R_SH_PLT32: usize = 161; +pub const R_SH_COPY: usize = 162; +pub const R_SH_GLOB_DAT: usize = 163; +pub const R_SH_JMP_SLOT: usize = 164; +pub const R_SH_RELATIVE: usize = 165; +pub const R_SH_GOTOFF: usize = 166; +pub const R_SH_GOTPC: usize = 167; +pub const R_SH_NUM: usize = 256; +pub const EF_S390_HIGH_GPRS: usize = 1; +pub const R_390_NONE: usize = 0; +pub const R_390_8: usize = 1; +pub const R_390_12: usize = 2; +pub const R_390_16: usize = 3; +pub const R_390_32: usize = 4; +pub const R_390_PC32: usize = 5; +pub const R_390_GOT12: usize = 6; +pub const R_390_GOT32: usize = 7; +pub const R_390_PLT32: usize = 8; +pub const R_390_COPY: usize = 9; +pub const R_390_GLOB_DAT: usize = 10; +pub const R_390_JMP_SLOT: usize = 11; +pub const R_390_RELATIVE: usize = 12; +pub const R_390_GOTOFF32: usize = 13; +pub const R_390_GOTPC: usize = 14; +pub const R_390_GOT16: usize = 15; +pub const R_390_PC16: usize = 16; +pub const R_390_PC16DBL: usize = 17; +pub const R_390_PLT16DBL: usize = 18; +pub const R_390_PC32DBL: usize = 19; +pub const R_390_PLT32DBL: usize = 20; +pub const R_390_GOTPCDBL: usize = 21; +pub const R_390_64: usize = 22; +pub const R_390_PC64: usize = 23; +pub const R_390_GOT64: usize = 24; +pub const R_390_PLT64: usize = 25; +pub const R_390_GOTENT: usize = 26; +pub const R_390_GOTOFF16: usize = 27; +pub const R_390_GOTOFF64: usize = 28; +pub const R_390_GOTPLT12: usize = 29; +pub const R_390_GOTPLT16: usize = 30; +pub const R_390_GOTPLT32: usize = 31; +pub const R_390_GOTPLT64: usize = 32; +pub const R_390_GOTPLTENT: usize = 33; +pub const R_390_PLTOFF16: usize = 34; +pub const R_390_PLTOFF32: usize = 35; +pub const R_390_PLTOFF64: usize = 36; +pub const R_390_TLS_LOAD: usize = 37; +pub const R_390_TLS_GDCALL: usize = 38; +pub const R_390_TLS_LDCALL: usize = 39; +pub const R_390_TLS_GD32: usize = 40; +pub const R_390_TLS_GD64: usize = 41; +pub const R_390_TLS_GOTIE12: usize = 42; +pub const R_390_TLS_GOTIE32: usize = 43; +pub const R_390_TLS_GOTIE64: usize = 44; +pub const R_390_TLS_LDM32: usize = 45; +pub const R_390_TLS_LDM64: usize = 46; +pub const R_390_TLS_IE32: usize = 47; +pub const R_390_TLS_IE64: usize = 48; +pub const R_390_TLS_IEENT: usize = 49; +pub const R_390_TLS_LE32: usize = 50; +pub const R_390_TLS_LE64: usize = 51; +pub const R_390_TLS_LDO32: usize = 52; +pub const R_390_TLS_LDO64: usize = 53; +pub const R_390_TLS_DTPMOD: usize = 54; +pub const R_390_TLS_DTPOFF: usize = 55; +pub const R_390_TLS_TPOFF: usize = 56; +pub const R_390_20: usize = 57; +pub const R_390_GOT20: usize = 58; +pub const R_390_GOTPLT20: usize = 59; +pub const R_390_TLS_GOTIE20: usize = 60; +pub const R_390_IRELATIVE: usize = 61; +pub const R_390_NUM: usize = 62; +pub const R_CRIS_NONE: usize = 0; +pub const R_CRIS_8: usize = 1; +pub const R_CRIS_16: usize = 2; +pub const R_CRIS_32: usize = 3; +pub const R_CRIS_8_PCREL: usize = 4; +pub const R_CRIS_16_PCREL: usize = 5; +pub const R_CRIS_32_PCREL: usize = 6; +pub const R_CRIS_GNU_VTINHERIT: usize = 7; +pub const R_CRIS_GNU_VTENTRY: usize = 8; +pub const R_CRIS_COPY: usize = 9; +pub const R_CRIS_GLOB_DAT: usize = 10; +pub const R_CRIS_JUMP_SLOT: usize = 11; +pub const R_CRIS_RELATIVE: usize = 12; +pub const R_CRIS_16_GOT: usize = 13; +pub const R_CRIS_32_GOT: usize = 14; +pub const R_CRIS_16_GOTPLT: usize = 15; +pub const R_CRIS_32_GOTPLT: usize = 16; +pub const R_CRIS_32_GOTREL: usize = 17; +pub const R_CRIS_32_PLT_GOTREL: usize = 18; +pub const R_CRIS_32_PLT_PCREL: usize = 19; +pub const R_CRIS_NUM: usize = 20; +pub const R_X86_64_NONE: usize = 0; +pub const R_X86_64_64: usize = 1; +pub const R_X86_64_PC32: usize = 2; +pub const R_X86_64_GOT32: usize = 3; +pub const R_X86_64_PLT32: usize = 4; +pub const R_X86_64_COPY: usize = 5; +pub const R_X86_64_GLOB_DAT: usize = 6; +pub const R_X86_64_JUMP_SLOT: usize = 7; +pub const R_X86_64_RELATIVE: usize = 8; +pub const R_X86_64_GOTPCREL: usize = 9; +pub const R_X86_64_32: usize = 10; +pub const R_X86_64_32S: usize = 11; +pub const R_X86_64_16: usize = 12; +pub const R_X86_64_PC16: usize = 13; +pub const R_X86_64_8: usize = 14; +pub const R_X86_64_PC8: usize = 15; +pub const R_X86_64_DTPMOD64: usize = 16; +pub const R_X86_64_DTPOFF64: usize = 17; +pub const R_X86_64_TPOFF64: usize = 18; +pub const R_X86_64_TLSGD: usize = 19; +pub const R_X86_64_TLSLD: usize = 20; +pub const R_X86_64_DTPOFF32: usize = 21; +pub const R_X86_64_GOTTPOFF: usize = 22; +pub const R_X86_64_TPOFF32: usize = 23; +pub const R_X86_64_PC64: usize = 24; +pub const R_X86_64_GOTOFF64: usize = 25; +pub const R_X86_64_GOTPC32: usize = 26; +pub const R_X86_64_GOT64: usize = 27; +pub const R_X86_64_GOTPCREL64: usize = 28; +pub const R_X86_64_GOTPC64: usize = 29; +pub const R_X86_64_GOTPLT64: usize = 30; +pub const R_X86_64_PLTOFF64: usize = 31; +pub const R_X86_64_SIZE32: usize = 32; +pub const R_X86_64_SIZE64: usize = 33; +pub const R_X86_64_GOTPC32_TLSDESC: usize = 34; +pub const R_X86_64_TLSDESC_CALL: usize = 35; +pub const R_X86_64_TLSDESC: usize = 36; +pub const R_X86_64_IRELATIVE: usize = 37; +pub const R_X86_64_RELATIVE64: usize = 38; +pub const R_X86_64_NUM: usize = 39; +pub const R_MN10300_NONE: usize = 0; +pub const R_MN10300_32: usize = 1; +pub const R_MN10300_16: usize = 2; +pub const R_MN10300_8: usize = 3; +pub const R_MN10300_PCREL32: usize = 4; +pub const R_MN10300_PCREL16: usize = 5; +pub const R_MN10300_PCREL8: usize = 6; +pub const R_MN10300_GNU_VTINHERIT: usize = 7; +pub const R_MN10300_GNU_VTENTRY: usize = 8; +pub const R_MN10300_24: usize = 9; +pub const R_MN10300_GOTPC32: usize = 10; +pub const R_MN10300_GOTPC16: usize = 11; +pub const R_MN10300_GOTOFF32: usize = 12; +pub const R_MN10300_GOTOFF24: usize = 13; +pub const R_MN10300_GOTOFF16: usize = 14; +pub const R_MN10300_PLT32: usize = 15; +pub const R_MN10300_PLT16: usize = 16; +pub const R_MN10300_GOT32: usize = 17; +pub const R_MN10300_GOT24: usize = 18; +pub const R_MN10300_GOT16: usize = 19; +pub const R_MN10300_COPY: usize = 20; +pub const R_MN10300_GLOB_DAT: usize = 21; +pub const R_MN10300_JMP_SLOT: usize = 22; +pub const R_MN10300_RELATIVE: usize = 23; +pub const R_MN10300_TLS_GD: usize = 24; +pub const R_MN10300_TLS_LD: usize = 25; +pub const R_MN10300_TLS_LDO: usize = 26; +pub const R_MN10300_TLS_GOTIE: usize = 27; +pub const R_MN10300_TLS_IE: usize = 28; +pub const R_MN10300_TLS_LE: usize = 29; +pub const R_MN10300_TLS_DTPMOD: usize = 30; +pub const R_MN10300_TLS_DTPOFF: usize = 31; +pub const R_MN10300_TLS_TPOFF: usize = 32; +pub const R_MN10300_SYM_DIFF: usize = 33; +pub const R_MN10300_ALIGN: usize = 34; +pub const R_MN10300_NUM: usize = 35; +pub const R_M32R_NONE: usize = 0; +pub const R_M32R_16: usize = 1; +pub const R_M32R_32: usize = 2; +pub const R_M32R_24: usize = 3; +pub const R_M32R_10_PCREL: usize = 4; +pub const R_M32R_18_PCREL: usize = 5; +pub const R_M32R_26_PCREL: usize = 6; +pub const R_M32R_HI16_ULO: usize = 7; +pub const R_M32R_HI16_SLO: usize = 8; +pub const R_M32R_LO16: usize = 9; +pub const R_M32R_SDA16: usize = 10; +pub const R_M32R_GNU_VTINHERIT: usize = 11; +pub const R_M32R_GNU_VTENTRY: usize = 12; +pub const R_M32R_16_RELA: usize = 33; +pub const R_M32R_32_RELA: usize = 34; +pub const R_M32R_24_RELA: usize = 35; +pub const R_M32R_10_PCREL_RELA: usize = 36; +pub const R_M32R_18_PCREL_RELA: usize = 37; +pub const R_M32R_26_PCREL_RELA: usize = 38; +pub const R_M32R_HI16_ULO_RELA: usize = 39; +pub const R_M32R_HI16_SLO_RELA: usize = 40; +pub const R_M32R_LO16_RELA: usize = 41; +pub const R_M32R_SDA16_RELA: usize = 42; +pub const R_M32R_RELA_GNU_VTINHERIT: usize = 43; +pub const R_M32R_RELA_GNU_VTENTRY: usize = 44; +pub const R_M32R_REL32: usize = 45; +pub const R_M32R_GOT24: usize = 48; +pub const R_M32R_26_PLTREL: usize = 49; +pub const R_M32R_COPY: usize = 50; +pub const R_M32R_GLOB_DAT: usize = 51; +pub const R_M32R_JMP_SLOT: usize = 52; +pub const R_M32R_RELATIVE: usize = 53; +pub const R_M32R_GOTOFF: usize = 54; +pub const R_M32R_GOTPC24: usize = 55; +pub const R_M32R_GOT16_HI_ULO: usize = 56; +pub const R_M32R_GOT16_HI_SLO: usize = 57; +pub const R_M32R_GOT16_LO: usize = 58; +pub const R_M32R_GOTPC_HI_ULO: usize = 59; +pub const R_M32R_GOTPC_HI_SLO: usize = 60; +pub const R_M32R_GOTPC_LO: usize = 61; +pub const R_M32R_GOTOFF_HI_ULO: usize = 62; +pub const R_M32R_GOTOFF_HI_SLO: usize = 63; +pub const R_M32R_GOTOFF_LO: usize = 64; +pub const R_M32R_NUM: usize = 256; +pub const R_MICROBLAZE_NONE: usize = 0; +pub const R_MICROBLAZE_32: usize = 1; +pub const R_MICROBLAZE_32_PCREL: usize = 2; +pub const R_MICROBLAZE_64_PCREL: usize = 3; +pub const R_MICROBLAZE_32_PCREL_LO: usize = 4; +pub const R_MICROBLAZE_64: usize = 5; +pub const R_MICROBLAZE_32_LO: usize = 6; +pub const R_MICROBLAZE_SRO32: usize = 7; +pub const R_MICROBLAZE_SRW32: usize = 8; +pub const R_MICROBLAZE_64_NONE: usize = 9; +pub const R_MICROBLAZE_32_SYM_OP_SYM: usize = 10; +pub const R_MICROBLAZE_GNU_VTINHERIT: usize = 11; +pub const R_MICROBLAZE_GNU_VTENTRY: usize = 12; +pub const R_MICROBLAZE_GOTPC_64: usize = 13; +pub const R_MICROBLAZE_GOT_64: usize = 14; +pub const R_MICROBLAZE_PLT_64: usize = 15; +pub const R_MICROBLAZE_REL: usize = 16; +pub const R_MICROBLAZE_JUMP_SLOT: usize = 17; +pub const R_MICROBLAZE_GLOB_DAT: usize = 18; +pub const R_MICROBLAZE_GOTOFF_64: usize = 19; +pub const R_MICROBLAZE_GOTOFF_32: usize = 20; +pub const R_MICROBLAZE_COPY: usize = 21; +pub const R_MICROBLAZE_TLS: usize = 22; +pub const R_MICROBLAZE_TLSGD: usize = 23; +pub const R_MICROBLAZE_TLSLD: usize = 24; +pub const R_MICROBLAZE_TLSDTPMOD32: usize = 25; +pub const R_MICROBLAZE_TLSDTPREL32: usize = 26; +pub const R_MICROBLAZE_TLSDTPREL64: usize = 27; +pub const R_MICROBLAZE_TLSGOTTPREL32: usize = 28; +pub const R_MICROBLAZE_TLSTPREL32: usize = 29; +pub const R_TILEPRO_NONE: usize = 0; +pub const R_TILEPRO_32: usize = 1; +pub const R_TILEPRO_16: usize = 2; +pub const R_TILEPRO_8: usize = 3; +pub const R_TILEPRO_32_PCREL: usize = 4; +pub const R_TILEPRO_16_PCREL: usize = 5; +pub const R_TILEPRO_8_PCREL: usize = 6; +pub const R_TILEPRO_LO16: usize = 7; +pub const R_TILEPRO_HI16: usize = 8; +pub const R_TILEPRO_HA16: usize = 9; +pub const R_TILEPRO_COPY: usize = 10; +pub const R_TILEPRO_GLOB_DAT: usize = 11; +pub const R_TILEPRO_JMP_SLOT: usize = 12; +pub const R_TILEPRO_RELATIVE: usize = 13; +pub const R_TILEPRO_BROFF_X1: usize = 14; +pub const R_TILEPRO_JOFFLONG_X1: usize = 15; +pub const R_TILEPRO_JOFFLONG_X1_PLT: usize = 16; +pub const R_TILEPRO_IMM8_X0: usize = 17; +pub const R_TILEPRO_IMM8_Y0: usize = 18; +pub const R_TILEPRO_IMM8_X1: usize = 19; +pub const R_TILEPRO_IMM8_Y1: usize = 20; +pub const R_TILEPRO_MT_IMM15_X1: usize = 21; +pub const R_TILEPRO_MF_IMM15_X1: usize = 22; +pub const R_TILEPRO_IMM16_X0: usize = 23; +pub const R_TILEPRO_IMM16_X1: usize = 24; +pub const R_TILEPRO_IMM16_X0_LO: usize = 25; +pub const R_TILEPRO_IMM16_X1_LO: usize = 26; +pub const R_TILEPRO_IMM16_X0_HI: usize = 27; +pub const R_TILEPRO_IMM16_X1_HI: usize = 28; +pub const R_TILEPRO_IMM16_X0_HA: usize = 29; +pub const R_TILEPRO_IMM16_X1_HA: usize = 30; +pub const R_TILEPRO_IMM16_X0_PCREL: usize = 31; +pub const R_TILEPRO_IMM16_X1_PCREL: usize = 32; +pub const R_TILEPRO_IMM16_X0_LO_PCREL: usize = 33; +pub const R_TILEPRO_IMM16_X1_LO_PCREL: usize = 34; +pub const R_TILEPRO_IMM16_X0_HI_PCREL: usize = 35; +pub const R_TILEPRO_IMM16_X1_HI_PCREL: usize = 36; +pub const R_TILEPRO_IMM16_X0_HA_PCREL: usize = 37; +pub const R_TILEPRO_IMM16_X1_HA_PCREL: usize = 38; +pub const R_TILEPRO_IMM16_X0_GOT: usize = 39; +pub const R_TILEPRO_IMM16_X1_GOT: usize = 40; +pub const R_TILEPRO_IMM16_X0_GOT_LO: usize = 41; +pub const R_TILEPRO_IMM16_X1_GOT_LO: usize = 42; +pub const R_TILEPRO_IMM16_X0_GOT_HI: usize = 43; +pub const R_TILEPRO_IMM16_X1_GOT_HI: usize = 44; +pub const R_TILEPRO_IMM16_X0_GOT_HA: usize = 45; +pub const R_TILEPRO_IMM16_X1_GOT_HA: usize = 46; +pub const R_TILEPRO_MMSTART_X0: usize = 47; +pub const R_TILEPRO_MMEND_X0: usize = 48; +pub const R_TILEPRO_MMSTART_X1: usize = 49; +pub const R_TILEPRO_MMEND_X1: usize = 50; +pub const R_TILEPRO_SHAMT_X0: usize = 51; +pub const R_TILEPRO_SHAMT_X1: usize = 52; +pub const R_TILEPRO_SHAMT_Y0: usize = 53; +pub const R_TILEPRO_SHAMT_Y1: usize = 54; +pub const R_TILEPRO_DEST_IMM8_X1: usize = 55; +pub const R_TILEPRO_TLS_GD_CALL: usize = 60; +pub const R_TILEPRO_IMM8_X0_TLS_GD_ADD: usize = 61; +pub const R_TILEPRO_IMM8_X1_TLS_GD_ADD: usize = 62; +pub const R_TILEPRO_IMM8_Y0_TLS_GD_ADD: usize = 63; +pub const R_TILEPRO_IMM8_Y1_TLS_GD_ADD: usize = 64; +pub const R_TILEPRO_TLS_IE_LOAD: usize = 65; +pub const R_TILEPRO_IMM16_X0_TLS_GD: usize = 66; +pub const R_TILEPRO_IMM16_X1_TLS_GD: usize = 67; +pub const R_TILEPRO_IMM16_X0_TLS_GD_LO: usize = 68; +pub const R_TILEPRO_IMM16_X1_TLS_GD_LO: usize = 69; +pub const R_TILEPRO_IMM16_X0_TLS_GD_HI: usize = 70; +pub const R_TILEPRO_IMM16_X1_TLS_GD_HI: usize = 71; +pub const R_TILEPRO_IMM16_X0_TLS_GD_HA: usize = 72; +pub const R_TILEPRO_IMM16_X1_TLS_GD_HA: usize = 73; +pub const R_TILEPRO_IMM16_X0_TLS_IE: usize = 74; +pub const R_TILEPRO_IMM16_X1_TLS_IE: usize = 75; +pub const R_TILEPRO_IMM16_X0_TLS_IE_LO: usize = 76; +pub const R_TILEPRO_IMM16_X1_TLS_IE_LO: usize = 77; +pub const R_TILEPRO_IMM16_X0_TLS_IE_HI: usize = 78; +pub const R_TILEPRO_IMM16_X1_TLS_IE_HI: usize = 79; +pub const R_TILEPRO_IMM16_X0_TLS_IE_HA: usize = 80; +pub const R_TILEPRO_IMM16_X1_TLS_IE_HA: usize = 81; +pub const R_TILEPRO_TLS_DTPMOD32: usize = 82; +pub const R_TILEPRO_TLS_DTPOFF32: usize = 83; +pub const R_TILEPRO_TLS_TPOFF32: usize = 84; +pub const R_TILEPRO_IMM16_X0_TLS_LE: usize = 85; +pub const R_TILEPRO_IMM16_X1_TLS_LE: usize = 86; +pub const R_TILEPRO_IMM16_X0_TLS_LE_LO: usize = 87; +pub const R_TILEPRO_IMM16_X1_TLS_LE_LO: usize = 88; +pub const R_TILEPRO_IMM16_X0_TLS_LE_HI: usize = 89; +pub const R_TILEPRO_IMM16_X1_TLS_LE_HI: usize = 90; +pub const R_TILEPRO_IMM16_X0_TLS_LE_HA: usize = 91; +pub const R_TILEPRO_IMM16_X1_TLS_LE_HA: usize = 92; +pub const R_TILEPRO_GNU_VTINHERIT: usize = 128; +pub const R_TILEPRO_GNU_VTENTRY: usize = 129; +pub const R_TILEPRO_NUM: usize = 130; +pub const R_TILEGX_NONE: usize = 0; +pub const R_TILEGX_64: usize = 1; +pub const R_TILEGX_32: usize = 2; +pub const R_TILEGX_16: usize = 3; +pub const R_TILEGX_8: usize = 4; +pub const R_TILEGX_64_PCREL: usize = 5; +pub const R_TILEGX_32_PCREL: usize = 6; +pub const R_TILEGX_16_PCREL: usize = 7; +pub const R_TILEGX_8_PCREL: usize = 8; +pub const R_TILEGX_HW0: usize = 9; +pub const R_TILEGX_HW1: usize = 10; +pub const R_TILEGX_HW2: usize = 11; +pub const R_TILEGX_HW3: usize = 12; +pub const R_TILEGX_HW0_LAST: usize = 13; +pub const R_TILEGX_HW1_LAST: usize = 14; +pub const R_TILEGX_HW2_LAST: usize = 15; +pub const R_TILEGX_COPY: usize = 16; +pub const R_TILEGX_GLOB_DAT: usize = 17; +pub const R_TILEGX_JMP_SLOT: usize = 18; +pub const R_TILEGX_RELATIVE: usize = 19; +pub const R_TILEGX_BROFF_X1: usize = 20; +pub const R_TILEGX_JUMPOFF_X1: usize = 21; +pub const R_TILEGX_JUMPOFF_X1_PLT: usize = 22; +pub const R_TILEGX_IMM8_X0: usize = 23; +pub const R_TILEGX_IMM8_Y0: usize = 24; +pub const R_TILEGX_IMM8_X1: usize = 25; +pub const R_TILEGX_IMM8_Y1: usize = 26; +pub const R_TILEGX_DEST_IMM8_X1: usize = 27; +pub const R_TILEGX_MT_IMM14_X1: usize = 28; +pub const R_TILEGX_MF_IMM14_X1: usize = 29; +pub const R_TILEGX_MMSTART_X0: usize = 30; +pub const R_TILEGX_MMEND_X0: usize = 31; +pub const R_TILEGX_SHAMT_X0: usize = 32; +pub const R_TILEGX_SHAMT_X1: usize = 33; +pub const R_TILEGX_SHAMT_Y0: usize = 34; +pub const R_TILEGX_SHAMT_Y1: usize = 35; +pub const R_TILEGX_IMM16_X0_HW0: usize = 36; +pub const R_TILEGX_IMM16_X1_HW0: usize = 37; +pub const R_TILEGX_IMM16_X0_HW1: usize = 38; +pub const R_TILEGX_IMM16_X1_HW1: usize = 39; +pub const R_TILEGX_IMM16_X0_HW2: usize = 40; +pub const R_TILEGX_IMM16_X1_HW2: usize = 41; +pub const R_TILEGX_IMM16_X0_HW3: usize = 42; +pub const R_TILEGX_IMM16_X1_HW3: usize = 43; +pub const R_TILEGX_IMM16_X0_HW0_LAST: usize = 44; +pub const R_TILEGX_IMM16_X1_HW0_LAST: usize = 45; +pub const R_TILEGX_IMM16_X0_HW1_LAST: usize = 46; +pub const R_TILEGX_IMM16_X1_HW1_LAST: usize = 47; +pub const R_TILEGX_IMM16_X0_HW2_LAST: usize = 48; +pub const R_TILEGX_IMM16_X1_HW2_LAST: usize = 49; +pub const R_TILEGX_IMM16_X0_HW0_PCREL: usize = 50; +pub const R_TILEGX_IMM16_X1_HW0_PCREL: usize = 51; +pub const R_TILEGX_IMM16_X0_HW1_PCREL: usize = 52; +pub const R_TILEGX_IMM16_X1_HW1_PCREL: usize = 53; +pub const R_TILEGX_IMM16_X0_HW2_PCREL: usize = 54; +pub const R_TILEGX_IMM16_X1_HW2_PCREL: usize = 55; +pub const R_TILEGX_IMM16_X0_HW3_PCREL: usize = 56; +pub const R_TILEGX_IMM16_X1_HW3_PCREL: usize = 57; +pub const R_TILEGX_IMM16_X0_HW0_LAST_PCREL: usize = 58; +pub const R_TILEGX_IMM16_X1_HW0_LAST_PCREL: usize = 59; +pub const R_TILEGX_IMM16_X0_HW1_LAST_PCREL: usize = 60; +pub const R_TILEGX_IMM16_X1_HW1_LAST_PCREL: usize = 61; +pub const R_TILEGX_IMM16_X0_HW2_LAST_PCREL: usize = 62; +pub const R_TILEGX_IMM16_X1_HW2_LAST_PCREL: usize = 63; +pub const R_TILEGX_IMM16_X0_HW0_GOT: usize = 64; +pub const R_TILEGX_IMM16_X1_HW0_GOT: usize = 65; +pub const R_TILEGX_IMM16_X0_HW0_PLT_PCREL: usize = 66; +pub const R_TILEGX_IMM16_X1_HW0_PLT_PCREL: usize = 67; +pub const R_TILEGX_IMM16_X0_HW1_PLT_PCREL: usize = 68; +pub const R_TILEGX_IMM16_X1_HW1_PLT_PCREL: usize = 69; +pub const R_TILEGX_IMM16_X0_HW2_PLT_PCREL: usize = 70; +pub const R_TILEGX_IMM16_X1_HW2_PLT_PCREL: usize = 71; +pub const R_TILEGX_IMM16_X0_HW0_LAST_GOT: usize = 72; +pub const R_TILEGX_IMM16_X1_HW0_LAST_GOT: usize = 73; +pub const R_TILEGX_IMM16_X0_HW1_LAST_GOT: usize = 74; +pub const R_TILEGX_IMM16_X1_HW1_LAST_GOT: usize = 75; +pub const R_TILEGX_IMM16_X0_HW3_PLT_PCREL: usize = 76; +pub const R_TILEGX_IMM16_X1_HW3_PLT_PCREL: usize = 77; +pub const R_TILEGX_IMM16_X0_HW0_TLS_GD: usize = 78; +pub const R_TILEGX_IMM16_X1_HW0_TLS_GD: usize = 79; +pub const R_TILEGX_IMM16_X0_HW0_TLS_LE: usize = 80; +pub const R_TILEGX_IMM16_X1_HW0_TLS_LE: usize = 81; +pub const R_TILEGX_IMM16_X0_HW0_LAST_TLS_LE: usize = 82; +pub const R_TILEGX_IMM16_X1_HW0_LAST_TLS_LE: usize = 83; +pub const R_TILEGX_IMM16_X0_HW1_LAST_TLS_LE: usize = 84; +pub const R_TILEGX_IMM16_X1_HW1_LAST_TLS_LE: usize = 85; +pub const R_TILEGX_IMM16_X0_HW0_LAST_TLS_GD: usize = 86; +pub const R_TILEGX_IMM16_X1_HW0_LAST_TLS_GD: usize = 87; +pub const R_TILEGX_IMM16_X0_HW1_LAST_TLS_GD: usize = 88; +pub const R_TILEGX_IMM16_X1_HW1_LAST_TLS_GD: usize = 89; +pub const R_TILEGX_IMM16_X0_HW0_TLS_IE: usize = 92; +pub const R_TILEGX_IMM16_X1_HW0_TLS_IE: usize = 93; +pub const R_TILEGX_IMM16_X0_HW0_LAST_PLT_PCREL: usize = 94; +pub const R_TILEGX_IMM16_X1_HW0_LAST_PLT_PCREL: usize = 95; +pub const R_TILEGX_IMM16_X0_HW1_LAST_PLT_PCREL: usize = 96; +pub const R_TILEGX_IMM16_X1_HW1_LAST_PLT_PCREL: usize = 97; +pub const R_TILEGX_IMM16_X0_HW2_LAST_PLT_PCREL: usize = 98; +pub const R_TILEGX_IMM16_X1_HW2_LAST_PLT_PCREL: usize = 99; +pub const R_TILEGX_IMM16_X0_HW0_LAST_TLS_IE: usize = 100; +pub const R_TILEGX_IMM16_X1_HW0_LAST_TLS_IE: usize = 101; +pub const R_TILEGX_IMM16_X0_HW1_LAST_TLS_IE: usize = 102; +pub const R_TILEGX_IMM16_X1_HW1_LAST_TLS_IE: usize = 103; +pub const R_TILEGX_TLS_DTPMOD64: usize = 106; +pub const R_TILEGX_TLS_DTPOFF64: usize = 107; +pub const R_TILEGX_TLS_TPOFF64: usize = 108; +pub const R_TILEGX_TLS_DTPMOD32: usize = 109; +pub const R_TILEGX_TLS_DTPOFF32: usize = 110; +pub const R_TILEGX_TLS_TPOFF32: usize = 111; +pub const R_TILEGX_TLS_GD_CALL: usize = 112; +pub const R_TILEGX_IMM8_X0_TLS_GD_ADD: usize = 113; +pub const R_TILEGX_IMM8_X1_TLS_GD_ADD: usize = 114; +pub const R_TILEGX_IMM8_Y0_TLS_GD_ADD: usize = 115; +pub const R_TILEGX_IMM8_Y1_TLS_GD_ADD: usize = 116; +pub const R_TILEGX_TLS_IE_LOAD: usize = 117; +pub const R_TILEGX_IMM8_X0_TLS_ADD: usize = 118; +pub const R_TILEGX_IMM8_X1_TLS_ADD: usize = 119; +pub const R_TILEGX_IMM8_Y0_TLS_ADD: usize = 120; +pub const R_TILEGX_IMM8_Y1_TLS_ADD: usize = 121; +pub const R_TILEGX_GNU_VTINHERIT: usize = 128; +pub const R_TILEGX_GNU_VTENTRY: usize = 129; +pub const R_TILEGX_NUM: usize = 130; +pub const R_OR1K_NONE: u8 = 0; +pub const R_OR1K_32: u8 = 1; +pub const R_OR1K_16: u8 = 2; +pub const R_OR1K_8: u8 = 3; +pub const R_OR1K_LO_16_IN_INSN: u8 = 4; +pub const R_OR1K_HI_16_IN_INSN: u8 = 5; +pub const R_OR1K_INSN_REL_26: u8 = 6; +pub const R_OR1K_GNU_VTENTRY: u8 = 7; +pub const R_OR1K_GNU_VTINHERIT: u8 = 8; +pub const R_OR1K_32_PCREL: u8 = 9; +pub const R_OR1K_16_PCREL: u8 = 10; +pub const R_OR1K_8_PCREL: u8 = 11; +pub const R_OR1K_GOTPC_HI16: u8 = 12; +pub const R_OR1K_GOTPC_LO16: u8 = 13; +pub const R_OR1K_GOT16: u8 = 14; +pub const R_OR1K_PLT26: u8 = 15; +pub const R_OR1K_GOTOFF_HI16: u8 = 16; +pub const R_OR1K_GOTOFF_LO16: u8 = 17; +pub const R_OR1K_COPY: u8 = 18; +pub const R_OR1K_GLOB_DAT: u8 = 19; +pub const R_OR1K_JMP_SLOT: u8 = 20; +pub const R_OR1K_RELATIVE: u8 = 21; +pub const R_OR1K_TLS_GD_HI16: u8 = 22; +pub const R_OR1K_TLS_GD_LO16: u8 = 23; +pub const R_OR1K_TLS_LDM_HI16: u8 = 24; +pub const R_OR1K_TLS_LDM_LO16: u8 = 25; +pub const R_OR1K_TLS_LDO_HI16: u8 = 26; +pub const R_OR1K_TLS_LDO_LO16: u8 = 27; +pub const R_OR1K_TLS_IE_HI16: u8 = 28; +pub const R_OR1K_TLS_IE_LO16: u8 = 29; +pub const R_OR1K_TLS_LE_HI16: u8 = 30; +pub const R_OR1K_TLS_LE_LO16: u8 = 31; +pub const R_OR1K_TLS_TPOFF: u8 = 32; +pub const R_OR1K_TLS_DTPOFF: u8 = 33; +pub const R_OR1K_TLS_DTPMOD: u8 = 34; +pub const R_OR1K_NUM: u8 = 35; + +pub type Elf32_Half = u16; +pub type Elf64_Half = u16; +pub type Elf32_Word = u32; +pub type Elf32_Sword = i32; +pub type Elf64_Word = u32; +pub type Elf64_Sword = i32; +pub type Elf32_Xword = u64; +pub type Elf32_Sxword = i64; +pub type Elf64_Xword = u64; +pub type Elf64_Sxword = i64; +pub type Elf32_Addr = u32; +pub type Elf64_Addr = u64; +pub type Elf32_Off = u32; +pub type Elf64_Off = u64; +pub type Elf32_Section = u16; +pub type Elf64_Section = u16; +pub type Elf32_Versym = Elf32_Half; +pub type Elf64_Versym = Elf64_Half; + +#[repr(C)] +#[derive(Debug, Copy)] +pub struct Elf32_Ehdr { + pub e_ident: [u8; 16usize], + pub e_type: Elf32_Half, + pub e_machine: Elf32_Half, + pub e_version: Elf32_Word, + pub e_entry: Elf32_Addr, + pub e_phoff: Elf32_Off, + pub e_shoff: Elf32_Off, + pub e_flags: Elf32_Word, + pub e_ehsize: Elf32_Half, + pub e_phentsize: Elf32_Half, + pub e_phnum: Elf32_Half, + pub e_shentsize: Elf32_Half, + pub e_shnum: Elf32_Half, + pub e_shstrndx: Elf32_Half, +} +impl Clone for Elf32_Ehdr { + fn clone(&self) -> Self { *self } +} +#[repr(C)] +#[derive(Debug, Copy)] +pub struct Elf64_Ehdr { + pub e_ident: [u8; 16usize], + pub e_type: Elf64_Half, + pub e_machine: Elf64_Half, + pub e_version: Elf64_Word, + pub e_entry: Elf64_Addr, + pub e_phoff: Elf64_Off, + pub e_shoff: Elf64_Off, + pub e_flags: Elf64_Word, + pub e_ehsize: Elf64_Half, + pub e_phentsize: Elf64_Half, + pub e_phnum: Elf64_Half, + pub e_shentsize: Elf64_Half, + pub e_shnum: Elf64_Half, + pub e_shstrndx: Elf64_Half, +} +impl Clone for Elf64_Ehdr { + fn clone(&self) -> Self { *self } +} +#[repr(C)] +#[derive(Debug, Copy)] +pub struct Elf32_Shdr { + pub sh_name: Elf32_Word, + pub sh_type: Elf32_Word, + pub sh_flags: Elf32_Word, + pub sh_addr: Elf32_Addr, + pub sh_offset: Elf32_Off, + pub sh_size: Elf32_Word, + pub sh_link: Elf32_Word, + pub sh_info: Elf32_Word, + pub sh_addralign: Elf32_Word, + pub sh_entsize: Elf32_Word, +} +impl Clone for Elf32_Shdr { + fn clone(&self) -> Self { *self } +} +#[repr(C)] +#[derive(Debug, Copy)] +pub struct Elf64_Shdr { + pub sh_name: Elf64_Word, + pub sh_type: Elf64_Word, + pub sh_flags: Elf64_Xword, + pub sh_addr: Elf64_Addr, + pub sh_offset: Elf64_Off, + pub sh_size: Elf64_Xword, + pub sh_link: Elf64_Word, + pub sh_info: Elf64_Word, + pub sh_addralign: Elf64_Xword, + pub sh_entsize: Elf64_Xword, +} +impl Clone for Elf64_Shdr { + fn clone(&self) -> Self { *self } +} +#[repr(C)] +#[derive(Debug, Copy)] +pub struct Elf32_Sym { + pub st_name: Elf32_Word, + pub st_value: Elf32_Addr, + pub st_size: Elf32_Word, + pub st_info: u8, + pub st_other: u8, + pub st_shndx: Elf32_Section, +} +impl Clone for Elf32_Sym { + fn clone(&self) -> Self { *self } +} +#[repr(C)] +#[derive(Debug, Copy)] +pub struct Elf64_Sym { + pub st_name: Elf64_Word, + pub st_info: u8, + pub st_other: u8, + pub st_shndx: Elf64_Section, + pub st_value: Elf64_Addr, + pub st_size: Elf64_Xword, +} +impl Clone for Elf64_Sym { + fn clone(&self) -> Self { *self } +} +#[repr(C)] +#[derive(Debug, Copy)] +pub struct Elf32_Syminfo { + pub si_boundto: Elf32_Half, + pub si_flags: Elf32_Half, +} +impl Clone for Elf32_Syminfo { + fn clone(&self) -> Self { *self } +} +#[repr(C)] +#[derive(Debug, Copy)] +pub struct Elf64_Syminfo { + pub si_boundto: Elf64_Half, + pub si_flags: Elf64_Half, +} +impl Clone for Elf64_Syminfo { + fn clone(&self) -> Self { *self } +} +#[repr(C)] +#[derive(Debug, Copy)] +pub struct Elf32_Rel { + pub r_offset: Elf32_Addr, + pub r_info: Elf32_Word, +} +impl Clone for Elf32_Rel { + fn clone(&self) -> Self { *self } +} +#[repr(C)] +#[derive(Debug, Copy)] +pub struct Elf64_Rel { + pub r_offset: Elf64_Addr, + pub r_info: Elf64_Xword, +} +impl Clone for Elf64_Rel { + fn clone(&self) -> Self { *self } +} +#[repr(C)] +#[derive(Debug, Copy)] +pub struct Elf32_Rela { + pub r_offset: Elf32_Addr, + pub r_info: Elf32_Word, + pub r_addend: Elf32_Sword, +} +impl Clone for Elf32_Rela { + fn clone(&self) -> Self { *self } +} +#[repr(C)] +#[derive(Debug, Copy)] +pub struct Elf64_Rela { + pub r_offset: Elf64_Addr, + pub r_info: Elf64_Xword, + pub r_addend: Elf64_Sxword, +} +impl Clone for Elf64_Rela { + fn clone(&self) -> Self { *self } +} +#[repr(C)] +#[derive(Debug, Copy)] +pub struct Elf32_Phdr { + pub p_type: Elf32_Word, + pub p_offset: Elf32_Off, + pub p_vaddr: Elf32_Addr, + pub p_paddr: Elf32_Addr, + pub p_filesz: Elf32_Word, + pub p_memsz: Elf32_Word, + pub p_flags: Elf32_Word, + pub p_align: Elf32_Word, +} +impl Clone for Elf32_Phdr { + fn clone(&self) -> Self { *self } +} +#[repr(C)] +#[derive(Debug, Copy)] +pub struct Elf64_Phdr { + pub p_type: Elf64_Word, + pub p_flags: Elf64_Word, + pub p_offset: Elf64_Off, + pub p_vaddr: Elf64_Addr, + pub p_paddr: Elf64_Addr, + pub p_filesz: Elf64_Xword, + pub p_memsz: Elf64_Xword, + pub p_align: Elf64_Xword, +} +impl Clone for Elf64_Phdr { + fn clone(&self) -> Self { *self } +} +#[repr(C)] +#[derive(Copy)] +pub struct Elf32_Dyn { + pub d_tag: Elf32_Sword, + pub d_un: Elf32_Dyn__bindgen_ty_1, +} +#[repr(C)] +#[derive(Copy)] +pub union Elf32_Dyn__bindgen_ty_1 { + pub d_val: Elf32_Word, + pub d_ptr: Elf32_Addr, +} +impl Clone for Elf32_Dyn__bindgen_ty_1 { + fn clone(&self) -> Self { *self } +} +impl Clone for Elf32_Dyn { + fn clone(&self) -> Self { *self } +} +#[repr(C)] +#[derive(Copy)] +pub struct Elf64_Dyn { + pub d_tag: Elf64_Sxword, + pub d_un: Elf64_Dyn__bindgen_ty_1, +} +#[repr(C)] +#[derive(Copy)] +pub union Elf64_Dyn__bindgen_ty_1 { + pub d_val: Elf64_Xword, + pub d_ptr: Elf64_Addr, +} +impl Clone for Elf64_Dyn__bindgen_ty_1 { + fn clone(&self) -> Self { *self } +} +impl Clone for Elf64_Dyn { + fn clone(&self) -> Self { *self } +} +#[repr(C)] +#[derive(Debug, Copy)] +pub struct Elf32_Verdef { + pub vd_version: Elf32_Half, + pub vd_flags: Elf32_Half, + pub vd_ndx: Elf32_Half, + pub vd_cnt: Elf32_Half, + pub vd_hash: Elf32_Word, + pub vd_aux: Elf32_Word, + pub vd_next: Elf32_Word, +} +impl Clone for Elf32_Verdef { + fn clone(&self) -> Self { *self } +} +#[repr(C)] +#[derive(Debug, Copy)] +pub struct Elf64_Verdef { + pub vd_version: Elf64_Half, + pub vd_flags: Elf64_Half, + pub vd_ndx: Elf64_Half, + pub vd_cnt: Elf64_Half, + pub vd_hash: Elf64_Word, + pub vd_aux: Elf64_Word, + pub vd_next: Elf64_Word, +} +impl Clone for Elf64_Verdef { + fn clone(&self) -> Self { *self } +} +#[repr(C)] +#[derive(Debug, Copy)] +pub struct Elf32_Verdaux { + pub vda_name: Elf32_Word, + pub vda_next: Elf32_Word, +} +impl Clone for Elf32_Verdaux { + fn clone(&self) -> Self { *self } +} +#[repr(C)] +#[derive(Debug, Copy)] +pub struct Elf64_Verdaux { + pub vda_name: Elf64_Word, + pub vda_next: Elf64_Word, +} +impl Clone for Elf64_Verdaux { + fn clone(&self) -> Self { *self } +} +#[repr(C)] +#[derive(Debug, Copy)] +pub struct Elf32_Verneed { + pub vn_version: Elf32_Half, + pub vn_cnt: Elf32_Half, + pub vn_file: Elf32_Word, + pub vn_aux: Elf32_Word, + pub vn_next: Elf32_Word, +} +impl Clone for Elf32_Verneed { + fn clone(&self) -> Self { *self } +} +#[repr(C)] +#[derive(Debug, Copy)] +pub struct Elf64_Verneed { + pub vn_version: Elf64_Half, + pub vn_cnt: Elf64_Half, + pub vn_file: Elf64_Word, + pub vn_aux: Elf64_Word, + pub vn_next: Elf64_Word, +} +impl Clone for Elf64_Verneed { + fn clone(&self) -> Self { *self } +} +#[repr(C)] +#[derive(Debug, Copy)] +pub struct Elf32_Vernaux { + pub vna_hash: Elf32_Word, + pub vna_flags: Elf32_Half, + pub vna_other: Elf32_Half, + pub vna_name: Elf32_Word, + pub vna_next: Elf32_Word, +} +impl Clone for Elf32_Vernaux { + fn clone(&self) -> Self { *self } +} +#[repr(C)] +#[derive(Debug, Copy)] +pub struct Elf64_Vernaux { + pub vna_hash: Elf64_Word, + pub vna_flags: Elf64_Half, + pub vna_other: Elf64_Half, + pub vna_name: Elf64_Word, + pub vna_next: Elf64_Word, +} +impl Clone for Elf64_Vernaux { + fn clone(&self) -> Self { *self } +} +#[repr(C)] +#[derive(Copy)] +pub struct Elf32_auxv_t { + pub a_type: u32, + pub a_un: Elf32_auxv_t__bindgen_ty_1, +} +#[repr(C)] +#[derive(Copy)] +pub union Elf32_auxv_t__bindgen_ty_1 { + pub a_val: u32, +} +impl Clone for Elf32_auxv_t__bindgen_ty_1 { + fn clone(&self) -> Self { *self } +} +impl Clone for Elf32_auxv_t { + fn clone(&self) -> Self { *self } +} +#[repr(C)] +#[derive(Copy)] +pub struct Elf64_auxv_t { + pub a_type: u64, + pub a_un: Elf64_auxv_t__bindgen_ty_1, +} +#[repr(C)] +#[derive(Copy)] +pub union Elf64_auxv_t__bindgen_ty_1 { + pub a_val: u64, +} +impl Clone for Elf64_auxv_t__bindgen_ty_1 { + fn clone(&self) -> Self { *self } +} +impl Clone for Elf64_auxv_t { + fn clone(&self) -> Self { *self } +} +#[repr(C)] +#[derive(Debug, Copy)] +pub struct Elf32_Nhdr { + pub n_namesz: Elf32_Word, + pub n_descsz: Elf32_Word, + pub n_type: Elf32_Word, +} +impl Clone for Elf32_Nhdr { + fn clone(&self) -> Self { *self } +} +#[repr(C)] +#[derive(Debug, Copy)] +pub struct Elf64_Nhdr { + pub n_namesz: Elf64_Word, + pub n_descsz: Elf64_Word, + pub n_type: Elf64_Word, +} +impl Clone for Elf64_Nhdr { + fn clone(&self) -> Self { *self } +} +#[repr(C)] +#[derive(Debug, Copy)] +pub struct Elf32_Move { + pub m_value: Elf32_Xword, + pub m_info: Elf32_Word, + pub m_poffset: Elf32_Word, + pub m_repeat: Elf32_Half, + pub m_stride: Elf32_Half, +} +impl Clone for Elf32_Move { + fn clone(&self) -> Self { *self } +} +#[repr(C)] +#[derive(Debug, Copy)] +pub struct Elf64_Move { + pub m_value: Elf64_Xword, + pub m_info: Elf64_Xword, + pub m_poffset: Elf64_Xword, + pub m_repeat: Elf64_Half, + pub m_stride: Elf64_Half, +} +impl Clone for Elf64_Move { + fn clone(&self) -> Self { *self } +} +#[repr(C)] +#[derive(Copy)] +pub union Elf32_gptab { + pub gt_header: Elf32_gptab__bindgen_ty_1, + pub gt_entry: Elf32_gptab__bindgen_ty_2, +} +#[repr(C)] +#[derive(Debug, Copy)] +pub struct Elf32_gptab__bindgen_ty_1 { + pub gt_current_g_value: Elf32_Word, + pub gt_unused: Elf32_Word, +} +impl Clone for Elf32_gptab__bindgen_ty_1 { + fn clone(&self) -> Self { *self } +} +#[repr(C)] +#[derive(Debug, Copy)] +pub struct Elf32_gptab__bindgen_ty_2 { + pub gt_g_value: Elf32_Word, + pub gt_bytes: Elf32_Word, +} +impl Clone for Elf32_gptab__bindgen_ty_2 { + fn clone(&self) -> Self { *self } +} +impl Clone for Elf32_gptab { + fn clone(&self) -> Self { *self } +} +#[repr(C)] +#[derive(Debug, Copy)] +pub struct Elf32_RegInfo { + pub ri_gprmask: Elf32_Word, + pub ri_cprmask: [Elf32_Word; 4usize], + pub ri_gp_value: Elf32_Sword, +} +impl Clone for Elf32_RegInfo { + fn clone(&self) -> Self { *self } +} +#[repr(C)] +#[derive(Debug, Copy)] +pub struct Elf_Options { + pub kind: u8, + pub size: u8, + pub section: Elf32_Section, + pub info: Elf32_Word, +} +impl Clone for Elf_Options { + fn clone(&self) -> Self { *self } +} +#[repr(C)] +#[derive(Debug, Copy)] +pub struct Elf_Options_Hw { + pub hwp_flags1: Elf32_Word, + pub hwp_flags2: Elf32_Word, +} +impl Clone for Elf_Options_Hw { + fn clone(&self) -> Self { *self } +} +#[repr(C)] +#[derive(Debug, Copy)] +pub struct Elf32_Lib { + pub l_name: Elf32_Word, + pub l_time_stamp: Elf32_Word, + pub l_checksum: Elf32_Word, + pub l_version: Elf32_Word, + pub l_flags: Elf32_Word, +} +impl Clone for Elf32_Lib { + fn clone(&self) -> Self { *self } +} +#[repr(C)] +#[derive(Debug, Copy)] +pub struct Elf64_Lib { + pub l_name: Elf64_Word, + pub l_time_stamp: Elf64_Word, + pub l_checksum: Elf64_Word, + pub l_version: Elf64_Word, + pub l_flags: Elf64_Word, +} +impl Clone for Elf64_Lib { + fn clone(&self) -> Self { *self } +} +pub type Elf32_Conflict = Elf32_Addr; + +pub fn ELF32_R_SYM(info: Elf32_Word) -> Elf32_Word { info >> 8 } +pub fn ELF32_R_TYPE(info: Elf32_Word) -> u8 { info as u8 } +pub fn ELF32_R_INFO(sym: Elf32_Word, ty: u8) -> Elf32_Word { sym << 8 | ty as Elf32_Word } + +pub fn ELF32_ST_BIND(info: u8) -> u8 { info >> 4 } +pub fn ELF32_ST_TYPE(info: u8) -> u8 { info & 0xf } +pub fn ELF32_ST_INFO(bind: u8, ty: u8) -> u8 { (bind << 4) | (ty & 0xf) } diff --git a/firmware/libdyld/lib.rs b/firmware/libdyld/lib.rs new file mode 100644 index 0000000..d16dc1c --- /dev/null +++ b/firmware/libdyld/lib.rs @@ -0,0 +1,339 @@ +#![no_std] + +use core::{mem, ptr, fmt, slice, str, convert}; +use elf::*; + +pub mod elf; + +fn read_unaligned(data: &[u8], offset: usize) -> Result { + if data.len() < offset + mem::size_of::() { + Err(()) + } else { + let ptr = data.as_ptr().wrapping_offset(offset as isize) as *const T; + Ok(unsafe { ptr::read_unaligned(ptr) }) + } +} + +fn get_ref(data: &[u8], offset: usize) -> Result<&T, ()> { + if data.len() < offset + mem::size_of::() { + Err(()) + } else if (data.as_ptr() as usize + offset) & (mem::align_of::() - 1) != 0 { + Err(()) + } else { + let ptr = data.as_ptr().wrapping_offset(offset as isize) as *const T; + Ok(unsafe { &*ptr }) + } +} + +fn get_ref_slice(data: &[u8], offset: usize, len: usize) -> Result<&[T], ()> { + if data.len() < offset + mem::size_of::() * len { + Err(()) + } else if (data.as_ptr() as usize + offset) & (mem::align_of::() - 1) != 0 { + Err(()) + } else { + let ptr = data.as_ptr().wrapping_offset(offset as isize) as *const T; + Ok(unsafe { slice::from_raw_parts(ptr, len) }) + } +} + +fn elf_hash(name: &[u8]) -> u32 { + let mut h: u32 = 0; + for c in name { + h = (h << 4) + *c as u32; + let g = h & 0xf0000000; + if g != 0 { + h ^= g >> 24; + h &= !g; + } + } + h +} + +#[derive(Debug)] +pub enum Error<'a> { + Parsing(&'static str), + Lookup(&'a [u8]) +} + +impl<'a> convert::From<&'static str> for Error<'a> { + fn from(desc: &'static str) -> Error<'a> { + Error::Parsing(desc) + } +} + +impl<'a> fmt::Display for Error<'a> { + fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { + match self { + &Error::Parsing(desc) => + write!(f, "parse error: {}", desc), + &Error::Lookup(sym) => + match str::from_utf8(sym) { + Ok(sym) => write!(f, "symbol lookup error: {}", sym), + Err(_) => write!(f, "symbol lookup error: {:?}", sym) + } + } + } +} + +pub struct Library<'a> { + image_off: Elf32_Addr, + image_sz: usize, + strtab: &'a [u8], + symtab: &'a [Elf32_Sym], + pltrel: &'a [Elf32_Rela], + hash_bucket: &'a [Elf32_Word], + hash_chain: &'a [Elf32_Word], +} + +impl<'a> Library<'a> { + pub fn lookup(&self, name: &[u8]) -> Option { + let hash = elf_hash(name); + let mut index = self.hash_bucket[hash as usize % self.hash_bucket.len()] as usize; + + loop { + if index == STN_UNDEF { return None } + + let sym = &self.symtab[index]; + let sym_name_off = sym.st_name as usize; + match self.strtab.get(sym_name_off..sym_name_off + name.len()) { + Some(sym_name) if sym_name == name => { + if ELF32_ST_BIND(sym.st_info) & STB_GLOBAL == 0 { + return None + } + + match sym.st_shndx { + SHN_UNDEF => return None, + SHN_ABS => return Some(sym.st_value), + _ => return Some(self.image_off + sym.st_value) + } + } + _ => (), + } + + index = self.hash_chain[index] as usize; + } + } + + fn name_starting_at(&self, offset: usize) -> Result<&'a [u8], Error<'a>> { + let size = self.strtab.iter().skip(offset).position(|&x| x == 0) + .ok_or("symbol in symbol table not null-terminated")?; + Ok(self.strtab.get(offset..offset + size) + .ok_or("cannot read symbol name")?) + } + + fn update_rela(&self, rela: &Elf32_Rela, value: Elf32_Word) -> Result<(), Error<'a>> { + if rela.r_offset as usize + mem::size_of::() > self.image_sz { + return Err("relocation out of image bounds")? + } + + let ptr = (self.image_off + rela.r_offset) as *mut Elf32_Addr; + Ok(unsafe { *ptr = value }) + } + + // This is unsafe because it mutates global data (the PLT). + pub unsafe fn rebind(&self, name: &[u8], addr: Elf32_Word) -> Result<(), Error<'a>> { + for rela in self.pltrel.iter() { + match ELF32_R_TYPE(rela.r_info) { + R_OR1K_32 | R_OR1K_GLOB_DAT | R_OR1K_JMP_SLOT => { + let sym = self.symtab.get(ELF32_R_SYM(rela.r_info) as usize) + .ok_or("symbol out of bounds of symbol table")?; + let sym_name = self.name_starting_at(sym.st_name as usize)?; + + if sym_name == name { + self.update_rela(rela, addr)? + } + } + + // No associated symbols for other relocation types. + _ => () + } + } + Ok(()) + } + + fn resolve_rela(&self, rela: &Elf32_Rela, resolve: &Fn(&[u8]) -> Option) + -> Result<(), Error<'a>> { + let sym; + if ELF32_R_SYM(rela.r_info) == 0 { + sym = None; + } else { + sym = Some(self.symtab.get(ELF32_R_SYM(rela.r_info) as usize) + .ok_or("symbol out of bounds of symbol table")?) + } + + let value; + match ELF32_R_TYPE(rela.r_info) { + R_OR1K_NONE => + return Ok(()), + + R_OR1K_RELATIVE => + value = self.image_off + rela.r_addend as Elf32_Word, + + R_OR1K_32 | R_OR1K_GLOB_DAT | R_OR1K_JMP_SLOT => { + let sym = sym.ok_or("relocation requires an associated symbol")?; + let sym_name = self.name_starting_at(sym.st_name as usize)?; + + // First, try to resolve against itself. + match self.lookup(sym_name) { + Some(addr) => value = addr, + None => { + // Second, call the user-provided function. + match resolve(sym_name) { + Some(addr) => value = addr, + None => { + // We couldn't find it anywhere. + return Err(Error::Lookup(sym_name)) + } + } + } + } + } + + _ => return Err("unsupported relocation type")? + } + + self.update_rela(rela, value) + } + + pub fn load(data: &[u8], image: &'a mut [u8], resolve: &Fn(&[u8]) -> Option) + -> Result, Error<'a>> { + #![allow(unused_assignments)] + + let ehdr = read_unaligned::(data, 0) + .map_err(|()| "cannot read ELF header")?; + + const IDENT: [u8; EI_NIDENT] = [ + ELFMAG0, ELFMAG1, ELFMAG2, ELFMAG3, + ELFCLASS32, ELFDATA2MSB, EV_CURRENT, ELFOSABI_NONE, + /* ABI version */ 0, /* padding */ 0, 0, 0, 0, 0, 0, 0 + ]; + + #[cfg(target_arch = "or1k")] + const ARCH: u16 = EM_OPENRISC; + #[cfg(not(target_arch = "or1k"))] + const ARCH: u16 = EM_NONE; + + if ehdr.e_ident != IDENT || ehdr.e_type != ET_DYN || ehdr.e_machine != ARCH { + return Err("not a shared library for current architecture")? + } + + let mut dyn_off = None; + for i in 0..ehdr.e_phnum { + let phdr_off = ehdr.e_phoff as usize + mem::size_of::() * i as usize; + let phdr = read_unaligned::(data, phdr_off) + .map_err(|()| "cannot read program header")?; + + match phdr.p_type { + PT_LOAD => { + if (phdr.p_vaddr + phdr.p_filesz) as usize > image.len() || + (phdr.p_offset + phdr.p_filesz) as usize > data.len() { + return Err("program header requests an out of bounds load")? + } + let dst = image.get_mut(phdr.p_vaddr as usize.. + (phdr.p_vaddr + phdr.p_filesz) as usize) + .ok_or("cannot write to program header destination")?; + let src = data.get(phdr.p_offset as usize.. + (phdr.p_offset + phdr.p_filesz) as usize) + .ok_or("cannot read from program header source")?; + dst.copy_from_slice(src); + } + + PT_DYNAMIC => + dyn_off = Some(phdr.p_vaddr), + + _ => () + } + } + + let (mut strtab_off, mut strtab_sz) = (0, 0); + let (mut symtab_off, mut symtab_sz) = (0, 0); + let (mut rela_off, mut rela_sz) = (0, 0); + let (mut pltrel_off, mut pltrel_sz) = (0, 0); + let (mut hash_off, mut hash_sz) = (0, 0); + let mut sym_ent = 0; + let mut rela_ent = 0; + let mut nbucket = 0; + let mut nchain = 0; + + let dyn_off = dyn_off.ok_or("cannot find a dynamic header")?; + for i in 0.. { + let dyn_off = dyn_off as usize + i * mem::size_of::(); + let dyn = get_ref::(image, dyn_off) + .map_err(|()| "cannot read dynamic header")?; + + let val = unsafe { dyn.d_un.d_val } as usize; + match dyn.d_tag { + DT_NULL => break, + DT_REL => return Err("relocations with implicit addend are not supported")?, + DT_STRTAB => strtab_off = val, + DT_STRSZ => strtab_sz = val, + DT_SYMTAB => symtab_off = val, + DT_SYMENT => sym_ent = val, + DT_RELA => rela_off = val, + DT_RELASZ => rela_sz = val / mem::size_of::(), + DT_RELAENT => rela_ent = val, + DT_JMPREL => pltrel_off = val, + DT_PLTRELSZ => pltrel_sz = val / mem::size_of::(), + DT_HASH => { + nbucket = *get_ref::(image, val + 0) + .map_err(|()| "cannot read hash bucket count")? as usize; + nchain = *get_ref::(image, val + 4) + .map_err(|()| "cannot read hash chain count")? as usize; + hash_off = val + 8; + hash_sz = nbucket + nchain; + } + _ => () + } + } + + if sym_ent != mem::size_of::() { + return Err("incorrect symbol entry size")? + } + if rela_ent != mem::size_of::() { + return Err("incorrect relocation entry size")? + } + + // These are the same--there are as many chains as buckets, and the chains only contain + // the symbols that overflowed the bucket. + symtab_sz = nchain; + + // Drop the mutability. See also the comment below. + let image = &*image; + + let strtab = get_ref_slice::(image, strtab_off, strtab_sz) + .map_err(|()| "cannot read string table")?; + let symtab = get_ref_slice::(image, symtab_off, symtab_sz) + .map_err(|()| "cannot read symbol table")?; + let rela = get_ref_slice::(image, rela_off, rela_sz) + .map_err(|()| "cannot read rela entries")?; + let pltrel = get_ref_slice::(image, pltrel_off, pltrel_sz) + .map_err(|()| "cannot read pltrel entries")?; + let hash = get_ref_slice::(image, hash_off, hash_sz) + .map_err(|()| "cannot read hash entries")?; + + let library = Library { + image_off: image.as_ptr() as Elf32_Word, + image_sz: image.len(), + strtab: strtab, + symtab: symtab, + pltrel: pltrel, + hash_bucket: &hash[..nbucket], + hash_chain: &hash[nbucket..nbucket + nchain], + }; + + // If a borrow exists anywhere, the borrowed memory cannot be mutated except + // through that pointer or it's UB. However, we need to retain pointers + // to the symbol tables and relocations, and at the same time mutate the code + // to resolve the relocations. + // + // To avoid invoking UB, we drop the only pointer to the entire area (which is + // unique since it's a &mut); we retain pointers to the various tables, but + // we never write to the memory they refer to, so it's safe. + mem::drop(image); + + for r in rela { library.resolve_rela(r, resolve)? } + for r in pltrel { library.resolve_rela(r, resolve)? } + + Ok(library) + } +} diff --git a/firmware/libksupport/._eh.rs b/firmware/libksupport/._eh.rs new file mode 100644 index 0000000000000000000000000000000000000000..98bb3ed5d6087f2550586cd13a3a7f63668053ee GIT binary patch literal 4096 zcmZQz6=P>$Vqox1Ojhs@R)|o50+1L3ClDJkFz{^v(m+1nBL)UWIUt(=a103vVqn;+ z3emx^0;pUIO$#HC4;5EQ&d=3LEGWoH)yqvSNlZyBNwkX3_I2?rNzDx{PAv*aOfP0& zNGiz5EG{uHSik`>i4kN12*79v58`GRdz2mxfzc2c4S~@R7!85Z5Eu=C(GVC7fzc2c z4S~@R7*Qbr>LS9siE<$snZ*i4sm1xFMaiiOY57Ij3YmE&sd*)t`FV*sIh6`Isc9t& ZNjZsm*}%T=a0n<=|HFMG!yxznKLGiME|UNN literal 0 HcmV?d00001 diff --git a/firmware/libksupport/Cargo.toml b/firmware/libksupport/Cargo.toml new file mode 100755 index 0000000..c5c28aa --- /dev/null +++ b/firmware/libksupport/Cargo.toml @@ -0,0 +1,20 @@ +[package] +name = "ksupport" +version = "0.1.0" +authors = ["cjb "] + + +[build-dependencies] +cc = "1.0" + +[dependencies] +board_misoc = { path = "../libboard_misoc"} +cslice = { version = "0.3" } +unwind = { path = "../libunwind-rs" } +libc = { default-features = false } +volatile_cell = "1.0" + +[lib] +path="lib.rs" +name = "ksupport" + diff --git a/firmware/libksupport/api.rs b/firmware/libksupport/api.rs new file mode 100755 index 0000000..2c6f768 --- /dev/null +++ b/firmware/libksupport/api.rs @@ -0,0 +1,89 @@ +macro_rules! api { + ($i:ident) => ({ + extern { static $i: u8; } + api!($i = &$i as *const _) + }); + ($i:ident, $d:item) => ({ + $d + api!($i = $i) + }); + ($i:ident = $e:expr) => { + (stringify!($i), unsafe { $e as *const () }) + } +} + + +#[allow(unused_unsafe)] +static mut API: &'static [(&'static str, *const ())] = &[ + api!(__divsi3), + api!(__modsi3), + api!(__ledf2), + api!(__gedf2), + api!(__unorddf2), + api!(__eqdf2), + api!(__ltdf2), + api!(__nedf2), + api!(__gtdf2), + api!(__addsf3), + api!(__subsf3), + api!(__mulsf3), + api!(__divsf3), + api!(__lshrdi3), + api!(__muldi3), + api!(__divdi3), + api!(__ashldi3), + api!(__ashrdi3), + api!(__udivmoddi4), + api!(__floatsisf), + api!(__floatunsisf), + api!(__fixsfsi), + api!(__fixunssfsi), + api!(__adddf3), + api!(__subdf3), + api!(__muldf3), + api!(__divdf3), + api!(__floatsidf), + api!(__floatunsidf), + api!(__floatdidf), + api!(__fixdfsi), + api!(__fixdfdi), + api!(__fixunsdfsi), + api!(__udivdi3), + api!(__umoddi3), + api!(__moddi3), + api!(__powidf2), + + /* libc */ + // api!(abort = ::abort), + api!(memcmp, extern { fn memcmp(a: *const u8, b: *mut u8, size: usize); }), + + /* libm */ + api!(sqrt), + api!(round), + api!(floor), + + /* exceptions */ + api!(_Unwind_Resume = ::unwind::_Unwind_Resume), + api!(__artiq_personality = ::eh::personality), + api!(__artiq_raise = ::eh::raise), + api!(__artiq_reraise = ::eh::reraise), + + /* proxified syscalls */ + api!(core_log), + + api!(now = &::NOW as *const _), + + + /* direct syscalls */ + api!(rtio_init = ::rtio::init), + api!(rtio_get_counter = ::rtio::get_counter), + api!(rtio_log), + api!(rtio_output = ::rtio::output), + api!(rtio_output_wide = ::rtio::output_wide), + api!(rtio_input_timestamp = ::rtio::input_timestamp), + api!(rtio_input_data = ::rtio::input_data), + api!(rtio_input_data_timeout = ::rtio::input_data_timeout), + api!(rtio_input_timestamp_data = ::rtio::input_timestamp_data), + +]; + diff --git a/firmware/libksupport/build.rs b/firmware/libksupport/build.rs new file mode 100755 index 0000000..d089754 --- /dev/null +++ b/firmware/libksupport/build.rs @@ -0,0 +1,12 @@ +extern crate cc; + + +fn main() { + let glue_path = "glue.c"; + + println!("cargo:rerun-if-changed={}", glue_path); + + cc::Build::new() + .file(glue_path) + .compile("glue"); +} diff --git a/firmware/libksupport/eh.rs b/firmware/libksupport/eh.rs new file mode 100644 index 0000000..cb46e34 --- /dev/null +++ b/firmware/libksupport/eh.rs @@ -0,0 +1,602 @@ +// Portions of the code in this file are derived from code by: +// +// Copyright 2015 The Rust Project Developers. See the COPYRIGHT +// file at http://rust-lang.org/COPYRIGHT. +// +// Licensed under the Apache License, Version 2.0 or the MIT license +// , at your +// option. This file may not be copied, modified, or distributed +// except according to those terms. +#![allow(non_upper_case_globals, non_camel_case_types, dead_code)] + +use core::{ptr, mem}; +use cslice::CSlice; +use unwind as uw; +use libc::{c_int, c_void}; + +#[cfg(not(target_arch = "arm"))] +type _Unwind_Stop_Fn = extern "C" fn(version: c_int, + actions: uw::_Unwind_Action, + exception_class: uw::_Unwind_Exception_Class, + exception_object: *mut uw::_Unwind_Exception, + context: *mut uw::_Unwind_Context, + stop_parameter: *mut c_void) + -> uw::_Unwind_Reason_Code; + +#[cfg(target_arch = "arm")] +type _Unwind_Stop_Fn = extern "C" fn(state: uw::_Unwind_State, + exception_object: *mut uw::_Unwind_Exception, + context: *mut uw::_Unwind_Context) + -> uw::_Unwind_Reason_Code; + +extern { + fn _Unwind_ForcedUnwind(exception: *mut uw::_Unwind_Exception, + stop_fn: _Unwind_Stop_Fn, + stop_parameter: *mut c_void) -> uw::_Unwind_Reason_Code; +} + +const DW_EH_PE_omit: u8 = 0xFF; +const DW_EH_PE_absptr: u8 = 0x00; + +const DW_EH_PE_uleb128: u8 = 0x01; +const DW_EH_PE_udata2: u8 = 0x02; +const DW_EH_PE_udata4: u8 = 0x03; +const DW_EH_PE_udata8: u8 = 0x04; +const DW_EH_PE_sleb128: u8 = 0x09; +const DW_EH_PE_sdata2: u8 = 0x0A; +const DW_EH_PE_sdata4: u8 = 0x0B; +const DW_EH_PE_sdata8: u8 = 0x0C; + +const DW_EH_PE_pcrel: u8 = 0x10; +const DW_EH_PE_textrel: u8 = 0x20; +const DW_EH_PE_datarel: u8 = 0x30; +const DW_EH_PE_funcrel: u8 = 0x40; +const DW_EH_PE_aligned: u8 = 0x50; + +const DW_EH_PE_indirect: u8 = 0x80; + +#[derive(Clone)] +struct DwarfReader { + pub ptr: *const u8, +} + +impl DwarfReader { + fn new(ptr: *const u8) -> DwarfReader { + DwarfReader { ptr: ptr } + } + + // DWARF streams are packed, so e.g. a u32 would not necessarily be aligned + // on a 4-byte boundary. This may cause problems on platforms with strict + // alignment requirements. By wrapping data in a "packed" struct, we are + // telling the backend to generate "misalignment-safe" code. + unsafe fn read(&mut self) -> T { + let result = ptr::read_unaligned(self.ptr as *const T); + self.ptr = self.ptr.offset(mem::size_of::() as isize); + result + } + + // ULEB128 and SLEB128 encodings are defined in Section 7.6 - "Variable + // Length Data". + unsafe fn read_uleb128(&mut self) -> u64 { + let mut shift: usize = 0; + let mut result: u64 = 0; + let mut byte: u8; + loop { + byte = self.read::(); + result |= ((byte & 0x7F) as u64) << shift; + shift += 7; + if byte & 0x80 == 0 { + break; + } + } + result + } + + unsafe fn read_sleb128(&mut self) -> i64 { + let mut shift: usize = 0; + let mut result: u64 = 0; + let mut byte: u8; + loop { + byte = self.read::(); + result |= ((byte & 0x7F) as u64) << shift; + shift += 7; + if byte & 0x80 == 0 { + break; + } + } + // sign-extend + if shift < 8 * mem::size_of::() && (byte & 0x40) != 0 { + result |= (!0 as u64) << shift; + } + result as i64 + } + + unsafe fn read_encoded_pointer(&mut self, encoding: u8) -> usize { + fn round_up(unrounded: usize, align: usize) -> usize { + debug_assert!(align.is_power_of_two()); + (unrounded + align - 1) & !(align - 1) + } + + debug_assert!(encoding != DW_EH_PE_omit); + + // DW_EH_PE_aligned implies it's an absolute pointer value + if encoding == DW_EH_PE_aligned { + self.ptr = round_up(self.ptr as usize, mem::size_of::()) as *const u8; + return self.read::() + } + + let value_ptr = self.ptr; + let mut result = match encoding & 0x0F { + DW_EH_PE_absptr => self.read::(), + DW_EH_PE_uleb128 => self.read_uleb128() as usize, + DW_EH_PE_udata2 => self.read::() as usize, + DW_EH_PE_udata4 => self.read::() as usize, + DW_EH_PE_udata8 => self.read::() as usize, + DW_EH_PE_sleb128 => self.read_sleb128() as usize, + DW_EH_PE_sdata2 => self.read::() as usize, + DW_EH_PE_sdata4 => self.read::() as usize, + DW_EH_PE_sdata8 => self.read::() as usize, + _ => panic!(), + }; + + result += match encoding & 0x70 { + DW_EH_PE_absptr => 0, + // relative to address of the encoded value, despite the name + DW_EH_PE_pcrel => value_ptr as usize, + // DW_EH_PE_funcrel => { + // if context.func_start == 0 { + // return Err(()) + // } + // context.func_start + // } + // DW_EH_PE_textrel => (*context.get_text_start)(), + // DW_EH_PE_datarel => (*context.get_data_start)(), + _ => panic!(), + }; + + if encoding & DW_EH_PE_indirect != 0 { + result = *(result as *const usize); + } + + result + } +} + +fn encoding_size(encoding: u8) -> usize { + if encoding == DW_EH_PE_omit { + return 0 + } + + match encoding & 0x0F { + DW_EH_PE_absptr => mem::size_of::(), + DW_EH_PE_udata2 => 2, + DW_EH_PE_udata4 => 4, + DW_EH_PE_udata8 => 8, + DW_EH_PE_sdata2 => 2, + DW_EH_PE_sdata4 => 4, + DW_EH_PE_sdata8 => 8, + _ => panic!() + } +} + +pub enum EHAction { + None, + Cleanup(usize), + Catch(usize), + Terminate, +} + +unsafe fn find_eh_action(uw_exception: *mut uw::_Unwind_Exception, + context: *mut uw::_Unwind_Context) -> EHAction { + + let lsda = uw::_Unwind_GetLanguageSpecificData(context) as *const u8; + let func_start = uw::_Unwind_GetRegionStart(context); + + if lsda.is_null() { + return EHAction::None + } + + let mut reader = DwarfReader::new(lsda); + + let start_encoding = reader.read::(); + // base address for landing pad offsets + let lpad_base = if start_encoding != DW_EH_PE_omit { + reader.read_encoded_pointer(start_encoding) + } else { + func_start + }; + + let mut ttype_encoding = reader.read::(); + let ttype_encoding_size = encoding_size(ttype_encoding) as isize; + + let class_info; + if ttype_encoding != DW_EH_PE_omit { + // // FIXME: ARM-only override; refactor this into read_target2 or something. + // // Alternatively, pass --target2=rel. + // ttype_encoding = DW_EH_PE_pcrel | DW_EH_PE_indirect; + + let class_info_offset = reader.read_uleb128(); + class_info = reader.ptr.offset(class_info_offset as isize); + } else { + class_info = ptr::null(); + } + assert!(!class_info.is_null()); + + let call_site_encoding = reader.read::(); + let call_site_table_length = reader.read_uleb128(); + let action_table = reader.ptr.offset(call_site_table_length as isize); + + let ip = uw::_Unwind_GetIP(context) - 1; + let exception_info = &mut *(uw_exception as *mut ExceptionInfo); + let exn_name = &exception_info.exception.unwrap().name; + + while reader.ptr < action_table { + let cs_start = reader.read_encoded_pointer(call_site_encoding); + let cs_len = reader.read_encoded_pointer(call_site_encoding); + let cs_lpad = reader.read_encoded_pointer(call_site_encoding); + let cs_action = reader.read_uleb128(); + + if ip < func_start + cs_start { + // Callsite table is sorted by cs_start, so if we've passed the ip, we + // may stop searching. + break + } + if ip > func_start + cs_start + cs_len { + continue + } + + if cs_lpad == 0 { + return EHAction::None + } + + let lpad = lpad_base + cs_lpad; + if cs_action == 0 { + return EHAction::Cleanup(lpad) + } + + let action_entry = action_table.offset((cs_action - 1) as isize); + let mut action_reader = DwarfReader::new(action_entry); + loop { + let type_info_offset = action_reader.read_sleb128() as isize; + let action_offset = action_reader.clone().read_sleb128() as isize; + assert!(type_info_offset >= 0); + + if type_info_offset > 0 { + let type_info_ptr_ptr = class_info.offset(-type_info_offset * ttype_encoding_size); + let type_info_ptr = DwarfReader::new(type_info_ptr_ptr) + .read_encoded_pointer(ttype_encoding); + let type_info = *(type_info_ptr as *const CSlice); + + if type_info.as_ref() == exn_name.as_ref() { + return EHAction::Catch(lpad) + } + + if type_info.len() == 0 { + // This is a catch-all clause. We don't compare type_info_ptr with null here + // because, in PIC mode, the OR1K LLVM backend emits a literal zero + // encoded with DW_EH_PE_pcrel, which of course doesn't result in + // a proper null pointer. + return EHAction::Catch(lpad) + } + } + + if action_offset == 0 { + break + } else { + action_reader.ptr = action_reader.ptr.offset(action_offset) + } + } + + return EHAction::None + } + + // the function has a personality but no landing pads; this is fine + EHAction::None +} + +#[repr(C)] +#[derive(Clone, Copy)] +pub struct Exception<'a> { + pub name: CSlice<'a, u8>, + pub file: CSlice<'a, u8>, + pub line: u32, + pub column: u32, + pub function: CSlice<'a, u8>, + pub message: CSlice<'a, u8>, + pub param: [i64; 3] +} + +const EXCEPTION_CLASS: uw::_Unwind_Exception_Class = 0x4d_4c_42_53_41_52_54_51; /* 'MLBSARTQ' */ + +const MAX_BACKTRACE_SIZE: usize = 128; + +#[repr(C)] +struct ExceptionInfo { + uw_exception: uw::_Unwind_Exception, + exception: Option>, + handled: bool, + backtrace: [usize; MAX_BACKTRACE_SIZE], + backtrace_size: usize +} + +#[cfg(target_arch = "x86_64")] +const UNWIND_DATA_REG: (i32, i32) = (0, 1); // RAX, RDX + +#[cfg(target_arch = "arm")] +const UNWIND_DATA_REG: (i32, i32) = (0, 1); // R0, R1 + +#[cfg(any(target_arch = "or1k"))] +const UNWIND_DATA_REG: (i32, i32) = (3, 4); // R3, R4 + +// Personality routine for non-ARM-EHABI (which uses a slightly different ABI). +#[cfg(not(target_arch = "arm"))] +#[export_name="__artiq_personality"] +pub extern fn personality(version: c_int, + actions: uw::_Unwind_Action, + uw_exception_class: uw::_Unwind_Exception_Class, + uw_exception: *mut uw::_Unwind_Exception, + context: *mut uw::_Unwind_Context) + -> uw::_Unwind_Reason_Code { + unsafe { + if version != 1 || uw_exception_class != EXCEPTION_CLASS { + return uw::_URC_FATAL_PHASE1_ERROR + } + + let eh_action = find_eh_action(uw_exception, context); + if actions as u32 & uw::_UA_SEARCH_PHASE as u32 != 0 { + match eh_action { + EHAction::None | + EHAction::Cleanup(_) => return uw::_URC_CONTINUE_UNWIND, + EHAction::Catch(_) => return uw::_URC_HANDLER_FOUND, + EHAction::Terminate => return uw::_URC_FATAL_PHASE1_ERROR, + } + } else { + match eh_action { + EHAction::None => return uw::_URC_CONTINUE_UNWIND, + EHAction::Cleanup(lpad) | + EHAction::Catch(lpad) => { + if actions as u32 & uw::_UA_HANDLER_FRAME as u32 != 0 { + exception_info.handled = true + } + + // Pass a pair of the unwinder exception and ARTIQ exception + // (which immediately follows). + uw::_Unwind_SetGR(context, UNWIND_DATA_REG.0, + uw_exception as uw::_Unwind_Word); + uw::_Unwind_SetGR(context, UNWIND_DATA_REG.1, + exception as *const _ as uw::_Unwind_Word); + uw::_Unwind_SetIP(context, lpad); + return uw::_URC_INSTALL_CONTEXT; + } + EHAction::Terminate => return uw::_URC_FATAL_PHASE2_ERROR, + } + } + } +} + +// ARM EHABI personality routine. +// http://infocenter.arm.com/help/topic/com.arm.doc.ihi0038b/IHI0038B_ehabi.pdf +#[cfg(target_arch = "arm")] +#[export_name="__artiq_personality"] +unsafe extern "C" fn personality(state: uw::_Unwind_State, + exception_object: *mut uw::_Unwind_Exception, + context: *mut uw::_Unwind_Context) + -> uw::_Unwind_Reason_Code { + let state = state as c_int; + let action = state & uw::_US_ACTION_MASK as c_int; + let search_phase = if action == uw::_US_VIRTUAL_UNWIND_FRAME as c_int { + // Backtraces on ARM will call the personality routine with + // state == _US_VIRTUAL_UNWIND_FRAME | _US_FORCE_UNWIND. In those cases + // we want to continue unwinding the stack. + if state & uw::_US_FORCE_UNWIND as c_int != 0 { + return continue_unwind(exception_object, context); + } + true + } else if action == uw::_US_UNWIND_FRAME_STARTING as c_int { + false + } else if action == uw::_US_UNWIND_FRAME_RESUME as c_int { + return continue_unwind(exception_object, context); + } else { + return uw::_URC_FAILURE; + }; + + // The DWARF unwinder assumes that _Unwind_Context holds things like the function + // and LSDA pointers, however ARM EHABI places them into the exception object. + // To preserve signatures of functions like _Unwind_GetLanguageSpecificData(), which + // take only the context pointer, GCC personality routines stash a pointer to exception_object + // in the context, using location reserved for ARM's "scratch register" (r12). + uw::_Unwind_SetGR(context, + uw::UNWIND_POINTER_REG, + exception_object as uw::_Unwind_Ptr); + // ...A more principled approach would be to provide the full definition of ARM's + // _Unwind_Context in our libunwind bindings and fetch the required data from there directly, + // bypassing DWARF compatibility functions. + + let eh_action = find_eh_action(exception_object, context); + if search_phase { + match eh_action { + EHAction::None | + EHAction::Cleanup(_) => return continue_unwind(exception_object, context), + EHAction::Catch(_) => return uw::_URC_HANDLER_FOUND, + EHAction::Terminate => { + return uw::_URC_FAILURE + } + } + } else { + match eh_action { + EHAction::None => return continue_unwind(exception_object, context), + EHAction::Cleanup(lpad) | + EHAction::Catch(lpad) => { + let exception_info = &mut *(exception_object as *mut ExceptionInfo); + + match eh_action { + EHAction::Catch(_) => exception_info.handled = true, + _ => (), + } + + // Pass a pair of the unwinder exception and ARTIQ exception + // (which immediately follows). + let exception = &exception_info.exception.unwrap(); + uw::_Unwind_SetGR(context, UNWIND_DATA_REG.0, + exception_object as uw::_Unwind_Word); + uw::_Unwind_SetGR(context, UNWIND_DATA_REG.1, + exception as *const _ as uw::_Unwind_Word); + uw::_Unwind_SetIP(context, lpad); + return uw::_URC_INSTALL_CONTEXT; + }, + EHAction::Terminate => { + return uw::_URC_FAILURE + } + } + } + + // On ARM EHABI the personality routine is responsible for actually + // unwinding a single stack frame before returning (ARM EHABI Sec. 6.1). + unsafe fn continue_unwind(exception_object: *mut uw::_Unwind_Exception, + context: *mut uw::_Unwind_Context) + -> uw::_Unwind_Reason_Code { + if __gnu_unwind_frame(exception_object, context) == uw::_URC_NO_REASON { + uw::_URC_CONTINUE_UNWIND + } else { + uw::_URC_FAILURE + } + } + // Defined in libunwind, matching the GNU implementation in libgcc. + extern "C" { + fn __gnu_unwind_frame(exception_object: *mut uw::_Unwind_Exception, + context: *mut uw::_Unwind_Context) + -> uw::_Unwind_Reason_Code; + } +} + +extern fn cleanup(_unwind_code: uw::_Unwind_Reason_Code, + uw_exception: *mut uw::_Unwind_Exception) { + unsafe { + let exception_info = &mut *(uw_exception as *mut ExceptionInfo); + + exception_info.exception = None; + } +} + +#[cfg(not(target_arch = "arm"))] +extern fn uncaught_exception(_version: c_int, + actions: uw::_Unwind_Action, + _uw_exception_class: uw::_Unwind_Exception_Class, + uw_exception: *mut uw::_Unwind_Exception, + context: *mut uw::_Unwind_Context, + _stop_parameter: *mut c_void) + -> uw::_Unwind_Reason_Code { + unsafe { + let exception_info = &mut *(uw_exception as *mut ExceptionInfo); + + if exception_info.backtrace_size < exception_info.backtrace.len() { + let ip = uw::_Unwind_GetIP(context); + exception_info.backtrace[exception_info.backtrace_size] = ip; + exception_info.backtrace_size += 1; + } + + if actions as u32 & uw::_UA_END_OF_STACK as u32 != 0 { + ::terminate(&exception_info.exception.unwrap(), + exception_info.backtrace[..exception_info.backtrace_size].as_mut()) + } else { + uw::_URC_NO_REASON + } + } +} + +#[cfg(target_arch = "arm")] +extern "C" fn uncaught_exception(state: uw::_Unwind_State, + exception_object: *mut uw::_Unwind_Exception, + context: *mut uw::_Unwind_Context) + -> uw::_Unwind_Reason_Code { + unsafe { + let exception_info = &mut *(exception_object as *mut ExceptionInfo); + + if exception_info.backtrace_size < exception_info.backtrace.len() { + let ip = uw::_Unwind_GetIP(context); + exception_info.backtrace[exception_info.backtrace_size] = ip; + exception_info.backtrace_size += 1; + } + + // if actions as u32 & uw::_UA_END_OF_STACK as u32 != 0 { + // ::terminate(&exception_info.exception.unwrap(), + // exception_info.backtrace[..exception_info.backtrace_size].as_mut()) + // } else { + uw::_URC_NO_REASON + // } + } +} + +// We can unfortunately not use mem::zeroed in a static, so Option<> is used as a workaround. +// See https://github.com/rust-lang/rust/issues/39498. +static mut INFLIGHT: ExceptionInfo = ExceptionInfo { + uw_exception: uw::_Unwind_Exception { + exception_class: EXCEPTION_CLASS, + exception_cleanup: cleanup, + private: [0; uw::unwinder_private_data_size], + }, + exception: None, + handled: false, + backtrace: [0; MAX_BACKTRACE_SIZE], + backtrace_size: 0 +}; + +#[export_name="__artiq_raise"] +#[unwind(allowed)] +pub unsafe extern fn raise(exception: *const Exception) -> ! { + // Zing! The Exception<'a> to Exception<'static> transmute is not really sound in case + // the exception is ever captured. Fortunately, they currently aren't, and we save + // on the hassle of having to allocate exceptions somewhere except on stack. + INFLIGHT.exception = Some(mem::transmute::>(*exception)); + INFLIGHT.handled = false; + + let result = uw::_Unwind_RaiseException(&mut INFLIGHT.uw_exception); + if result != uw::_URC_END_OF_STACK { + println!("Unwinding error: {}", result as u32); + } + assert!(result == uw::_URC_END_OF_STACK); + + // INFLIGHT.backtrace_size = 0; + // let _result = _Unwind_ForcedUnwind(&mut INFLIGHT.uw_exception, + // uncaught_exception, ptr::null_mut()); + print!("Uncaught exception"); + loop {} + unreachable!() +} + +#[export_name="__artiq_reraise"] +#[unwind(allowed)] +pub unsafe extern fn reraise() -> ! { + if INFLIGHT.handled { + raise(&INFLIGHT.exception.unwrap()) + } else { + uw::_Unwind_Resume(&mut INFLIGHT.uw_exception) + } +} + +// Stub implementations for the functions the panic_unwind crate expects to be provided. +// These all do nothing in libunwind, but aren't built for OR1K. +#[cfg(target_arch = "or1k")] +pub mod stubs { + #![allow(bad_style, unused_variables)] + + use super::{uw, c_int}; + + #[export_name="_Unwind_GetIPInfo"] + pub unsafe extern fn _Unwind_GetIPInfo(ctx: *mut uw::_Unwind_Context, + ip_before_insn: *mut c_int) -> uw::_Unwind_Word { + *ip_before_insn = 0; + uw::_Unwind_GetIP(ctx) + } + + #[export_name="_Unwind_GetTextRelBase"] + pub unsafe extern fn _Unwind_GetTextRelBase(ctx: *mut uw::_Unwind_Context) -> uw::_Unwind_Ptr { + unimplemented!() + } + + #[export_name="_Unwind_GetDataRelBase"] + pub unsafe extern fn _Unwind_GetDataRelBase(ctx: *mut uw::_Unwind_Context) -> uw::_Unwind_Ptr { + unimplemented!() + } +} diff --git a/firmware/libksupport/glue.c b/firmware/libksupport/glue.c new file mode 100755 index 0000000..b48d0bd --- /dev/null +++ b/firmware/libksupport/glue.c @@ -0,0 +1,68 @@ +#include +#include +#include +#include +#include + +struct slice { + void *ptr; + size_t len; +}; + +void send_to_core_log(struct slice str); + +#define KERNELCPU_EXEC_ADDRESS 0x40800000 +#define KERNELCPU_PAYLOAD_ADDRESS 0x40840000 +#define KERNELCPU_LAST_ADDRESS 0x4fffffff +#define KSUPPORT_HEADER_SIZE 0x80 + + +/* called by kernel */ +double round(double x); +double round(double x) +{ + union {double f; uint64_t i;} u = {x}; + int e = u.i >> 52 & 0x7ff; + double y; + + if (e >= 0x3ff+52) + return x; + if (u.i >> 63) + x = -x; + if (e < 0x3ff-1) { + /* we don't do it in ARTIQ */ + /* raise inexact if x!=0 */ + // FORCE_EVAL(x + 0x1p52); + return 0*u.f; + } + y = (double)(x + 0x1p52) - 0x1p52 - x; + if (y > 0.5) + y = y + x - 1; + else if (y <= -0.5) + y = y + x + 1; + else + y = y + x; + if (u.i >> 63) + y = -y; + return y; +} + +/* called by kernel */ +int core_log(const char *fmt, ...); +int core_log(const char *fmt, ...) +{ + va_list args; + + va_start(args, fmt); + size_t size = vsnprintf(NULL, 0, fmt, args); + char *buf = __builtin_alloca(size + 1); + va_end(args); + + va_start(args, fmt); + vsnprintf(buf, size + 1, fmt, args); + va_end(args); + + struct slice str = { buf, size }; + send_to_core_log(str); + return 0; +} diff --git a/firmware/libksupport/lib.rs b/firmware/libksupport/lib.rs new file mode 100755 index 0000000..46f5b90 --- /dev/null +++ b/firmware/libksupport/lib.rs @@ -0,0 +1,59 @@ +#![feature(lang_items, asm, libc, panic_unwind, unwind_attributes, global_allocator, + needs_panic_runtime)] +#![no_std] + +extern crate unwind; +extern crate libc; +extern crate cslice; +#[macro_use] +extern crate board_misoc; +extern crate volatile_cell; + +use cslice::CSlice; +use core::str; + +#[no_mangle] +pub static mut now: u64 = 0; + +pub mod eh; + +#[no_mangle] +pub extern fn send_to_core_log(text: CSlice) { + match str::from_utf8(text.as_ref()) { + Ok(s) => print!("{}", s), + Err(_e) => println!("kernel send invalid utf8") + } +} + +fn terminate(exception: &eh::Exception, backtrace: &mut [usize]) -> ! { + print!("Uncaught exception"); + // at {}:{}: {}({})", + // str::from_utf8(exception.file.as_ref()).unwrap(), + // exception.line, + // str::from_utf8(exception.name.as_ref()).unwrap(), + // str::from_utf8(exception.message.as_ref()).unwrap()); + loop {} +} + +macro_rules! raise { + ($name:expr, $message:expr, $param0:expr, $param1:expr, $param2:expr) => ({ + use cslice::AsCSlice; + let exn = $crate::eh::Exception { + name: concat!("0:artiq.coredevice.exceptions.", $name).as_bytes().as_c_slice(), + file: file!().as_bytes().as_c_slice(), + line: line!(), + column: column!(), + // https://github.com/rust-lang/rfcs/pull/1719 + function: "(Rust function)".as_bytes().as_c_slice(), + message: $message.as_bytes().as_c_slice(), + param: [$param0, $param1, $param2] + }; + #[allow(unused_unsafe)] + unsafe { $crate::eh::raise(&exn) } + }); + ($name:expr, $message:expr) => ({ + raise!($name, $message, 0, 0, 0) + }); +} + +pub mod rtio; diff --git a/firmware/libksupport/rtio.rs b/firmware/libksupport/rtio.rs new file mode 100755 index 0000000..9b3305a --- /dev/null +++ b/firmware/libksupport/rtio.rs @@ -0,0 +1,337 @@ + + +use core::ptr::{read_volatile, write_volatile}; +use cslice::CSlice; +use board_misoc::csr; + +use volatile_cell::VolatileCell; + +pub const RTIO_O_STATUS_WAIT: u8 = 1; +pub const RTIO_O_STATUS_UNDERFLOW: u8 = 2; +pub const RTIO_O_STATUS_LINK_ERROR: u8 = 4; +pub const RTIO_I_STATUS_WAIT_EVENT: u8 = 1; +pub const RTIO_I_STATUS_OVERFLOW: u8 = 2; +pub const RTIO_I_STATUS_WAIT_STATUS: u8 = 4; +pub const RTIO_I_STATUS_LINK_ERROR: u8 = 8; + +#[repr(C)] +struct RtioCmd { + cmd_channel: i32, + address: i32, + timestamp: i64, + data: i64 +} + +#[repr(C)] +struct RtioResponse { + status: VolatileCell, + data: VolatileCell, + timestamp: VolatileCell +} + +pub const DMA_BASE: isize = 0x200000; + + + +#[no_mangle] +pub extern fn rtio_init() { + unsafe { + csr::rtio_core::reset_write(1); + csr::rtio_core::reset_phy_write(1); + } +} + +#[no_mangle] +pub extern fn rtio_get_counter() -> i64 { + unsafe { + csr::rtio::counter_update_write(1); + csr::rtio::counter_read() as i64 + } +} + +#[inline(always)] +pub unsafe fn rtio_o_data_write(offset: usize, data: u32) { + write_volatile( + csr::rtio::O_DATA_ADDR.offset((csr::rtio::O_DATA_SIZE - 1 - offset) as isize), + data); +} + +#[inline(always)] +pub unsafe fn rtio_i_data_read(offset: usize) -> u32 { + read_volatile( + csr::rtio::I_DATA_ADDR.offset((csr::rtio::I_DATA_SIZE - 1 - offset) as isize)) +} + +#[inline(never)] +unsafe fn process_exceptional_status(timestamp: i64, channel: i32, status: u8) { + if status & RTIO_O_STATUS_WAIT != 0 { + while csr::rtio::o_status_read() & RTIO_O_STATUS_WAIT != 0 {} + } + if status & RTIO_O_STATUS_UNDERFLOW != 0 { + raise!("RTIOUnderflow", + "RTIO underflow at {0} mu, channel {1}, slack {2} mu", + timestamp, channel as i64, timestamp - rtio_get_counter()); + } + if status & RTIO_O_STATUS_LINK_ERROR != 0 { + raise!("RTIOLinkError", + "RTIO output link error at {0} mu, channel {1}", + timestamp, channel as i64, 0); + } +} + +#[no_mangle] +pub extern fn rtio_output_csr(timestamp: i64, channel: i32, addr: i32, data: i32) { + unsafe { + csr::rtio::chan_sel_write(channel as _); + // writing timestamp clears o_data + csr::rtio::timestamp_write(timestamp as u64); + csr::rtio::o_address_write(addr as _); + rtio_o_data_write(0, data as _); + csr::rtio::o_we_write(1); + let status = csr::rtio::o_status_read(); + if status != 0 { + process_exceptional_status(timestamp, channel, status); + } + } +} + +#[no_mangle] +pub extern fn rtio_output(timestamp: i64, channel: i32, address: i32, data: i32) { + unsafe { + let rtio_cmd: *mut RtioCmd = DMA_BASE as *mut _; + let rtio_response: *mut RtioResponse = (DMA_BASE+0x20) as *mut _; + + // Clear status so we can observe response + (*rtio_response).status.set(0); + + (*rtio_cmd).cmd_channel = (0<<24) | channel; + (*rtio_cmd).address = address; + (*rtio_cmd).timestamp = timestamp; + (*rtio_cmd).data = data as i64; + + asm!("dmb"); + asm!("sev"); + + let mut status; + loop { + status = (*rtio_response).status.get(); + if status != 0 {break} + } + + let status = status & !0x10000; + if status != 0 {process_exceptional_status(timestamp, channel, status as u8)} + } +} + +#[no_mangle] +pub extern fn rtio_input_timestamp(timestamp: i64, channel: i32) -> u64 { + unsafe { + let rtio_cmd: *mut RtioCmd = DMA_BASE as *mut _; + let rtio_response: *mut RtioResponse = (DMA_BASE+0x20) as *mut _; + + // Clear status so we can observe response + (*rtio_response).status.set(0); + + (*rtio_cmd).cmd_channel = (1<<24) | channel; + (*rtio_cmd).timestamp = timestamp; + + asm!("dmb"); + asm!("sev"); + + let mut status; + loop { + status = (*rtio_response).status.get(); + if status != 0 {break} + } + + let status = status & !0x10000; + let status = status as u8; + + if status & RTIO_I_STATUS_OVERFLOW != 0 { + csr::cri_con::selected_write(0); + csr::rtio::i_overflow_reset_write(1); + csr::cri_con::selected_write(1); + raise!("RTIOOverflow", + "RTIO input overflow on channel {0}", + channel as i64, 0, 0); + } + if status & RTIO_I_STATUS_WAIT_EVENT != 0 { + return !0 + } + if status & RTIO_I_STATUS_LINK_ERROR != 0 { + raise!("RTIOLinkError", + "RTIO input link error on channel {0}", + channel as i64, 0, 0); + } + + (*rtio_response).timestamp.get() + } +} + + + + +#[no_mangle] +pub extern fn output_wide(timestamp: i64, channel: i32, addr: i32, data: CSlice) { + unsafe { + csr::rtio::chan_sel_write(channel as _); + // writing timestamp clears o_data + csr::rtio::timestamp_write(timestamp as u64); + csr::rtio::o_address_write(addr as _); + for i in 0..data.len() { + rtio_o_data_write(i, data[i] as _) + } + csr::rtio::o_we_write(1); + let status = csr::rtio::o_status_read(); + if status != 0 { + process_exceptional_status(timestamp, channel, status); + } + } +} + +#[no_mangle] +pub extern fn rtio_input_timestamp_csr(timeout: i64, channel: i32) -> u64 { + unsafe { + csr::rtio::chan_sel_write(channel as _); + csr::rtio::timestamp_write(timeout as u64); + csr::rtio::i_request_write(1); + + let mut status = RTIO_I_STATUS_WAIT_STATUS; + while status & RTIO_I_STATUS_WAIT_STATUS != 0 { + status = csr::rtio::i_status_read(); + } + + if status & RTIO_I_STATUS_OVERFLOW != 0 { + csr::rtio::i_overflow_reset_write(1); + raise!("RTIOOverflow", + "RTIO input overflow on channel {0}", + channel as i64, 0, 0); + } + if status & RTIO_I_STATUS_WAIT_EVENT != 0 { + return !0 + } + if status & RTIO_I_STATUS_LINK_ERROR != 0 { + raise!("RTIOLinkError", + "RTIO input link error on channel {0}", + channel as i64, 0, 0); + } + + csr::rtio::i_timestamp_read() + } +} + +#[no_mangle] +pub extern fn rtio_input_data(channel: i32) -> i32 { + unsafe { + csr::rtio::chan_sel_write(channel as _); + csr::rtio::timestamp_write(0xffffffff_ffffffff); + csr::rtio::i_request_write(1); + + let mut status = RTIO_I_STATUS_WAIT_STATUS; + while status & RTIO_I_STATUS_WAIT_STATUS != 0 { + status = csr::rtio::i_status_read(); + } + + if status & RTIO_I_STATUS_OVERFLOW != 0 { + csr::rtio::i_overflow_reset_write(1); + raise!("RTIOOverflow", + "RTIO input overflow on channel {0}", + channel as i64, 0, 0); + } + if status & RTIO_I_STATUS_LINK_ERROR != 0 { + raise!("RTIOLinkError", + "RTIO input link error on channel {0}", + channel as i64, 0, 0); + } + + rtio_i_data_read(0) as i32 + } +} + +#[no_mangle] +pub extern fn rtio_input_data_timeout(timeout: i64, channel: i32) -> i32 { + unsafe { + csr::rtio::chan_sel_write(channel as _); + csr::rtio::timestamp_write(timeout as u64); + csr::rtio::i_request_write(1); + + let mut status = RTIO_I_STATUS_WAIT_STATUS; + while status & RTIO_I_STATUS_WAIT_STATUS != 0 { + status = csr::rtio::i_status_read(); + } + + if status & RTIO_I_STATUS_OVERFLOW != 0 { + csr::rtio::i_overflow_reset_write(1); + raise!("RTIOOverflow", + "RTIO input overflow on channel {0}", + channel as i64, 0, 0); + } + + if status & RTIO_I_STATUS_WAIT_EVENT != 0 { + return !0 + } + + rtio_i_data_read(0) as i32 + } +} + + +#[repr(C)] +pub struct TimestampData { + timestamp: u64, + data: i32, +} + +pub extern fn input_timestamp_data(channel: i32) -> TimestampData { + unsafe { + csr::rtio::chan_sel_write(channel as _); + csr::rtio::timestamp_write(0xffffffff_ffffffff); + csr::rtio::i_request_write(1); + + let mut status = RTIO_I_STATUS_WAIT_STATUS; + while status & RTIO_I_STATUS_WAIT_STATUS != 0 { + status = csr::rtio::i_status_read(); + } + + if status & RTIO_I_STATUS_OVERFLOW != 0 { + csr::rtio::i_overflow_reset_write(1); + println!("RTIO input overflow on channel {0}",channel as i64); + } + + + TimestampData { + timestamp: csr::rtio::i_timestamp_read(), + data: rtio_i_data_read(0) as i32 + } + } +} + + +#[cfg(has_rtio_log)] +pub fn log(timestamp: i64, data: &[u8]) { + unsafe { + csr::rtio::chan_sel_write(csr::CONFIG_RTIO_LOG_CHANNEL); + csr::rtio::timestamp_write(timestamp as u64); + + let mut word: u32 = 0; + for i in 0..data.len() { + word <<= 8; + word |= data[i] as u32; + if i % 4 == 3 { + rtio_o_data_write(0, word); + csr::rtio::o_we_write(1); + word = 0; + } + } + + if word != 0 { + rtio_o_data_write(0, word); + csr::rtio::o_we_write(1); + } + } +} + +#[cfg(not(has_rtio_log))] +pub fn log(_timestamp: i64, _data: &[u8]) { + unimplemented!("not(has_rtio_log)") +} diff --git a/firmware/libunwind-rs/Cargo.toml b/firmware/libunwind-rs/Cargo.toml new file mode 100755 index 0000000..c7d9896 --- /dev/null +++ b/firmware/libunwind-rs/Cargo.toml @@ -0,0 +1,15 @@ +[package] +authors = ["The Rust Project Developers"] +name = "unwind" +version = "0.0.0" +build = "build.rs" + +[lib] +name = "unwind" +path = "lib.rs" +test = false +bench = false +doc = false + +[dependencies] +libc = { default-features = false } diff --git a/firmware/libunwind-rs/build.rs b/firmware/libunwind-rs/build.rs new file mode 100755 index 0000000..78aef41 --- /dev/null +++ b/firmware/libunwind-rs/build.rs @@ -0,0 +1,41 @@ +// Copyright 2016 The Rust Project Developers. See the COPYRIGHT +// file at the top-level directory of this distribution and at +// http://rust-lang.org/COPYRIGHT. +// +// Licensed under the Apache License, Version 2.0 or the MIT license +// , at your +// option. This file may not be copied, modified, or distributed +// except according to those terms. + +use std::env; + +fn main() { + println!("cargo:rustc-cfg=cargobuild"); + + let target = env::var("TARGET").expect("TARGET was not set"); + + if target.contains("linux") { + if target.contains("musl") && !target.contains("mips") { + println!("cargo:rustc-link-lib=static=unwind"); + } else if !target.contains("android") { + println!("cargo:rustc-link-lib=gcc_s"); + } + } else if target.contains("freebsd") { + println!("cargo:rustc-link-lib=gcc_s"); + } else if target.contains("rumprun") { + println!("cargo:rustc-link-lib=unwind"); + } else if target.contains("netbsd") { + println!("cargo:rustc-link-lib=gcc_s"); + } else if target.contains("openbsd") { + println!("cargo:rustc-link-lib=gcc"); + } else if target.contains("bitrig") { + println!("cargo:rustc-link-lib=c++abi"); + } else if target.contains("dragonfly") { + println!("cargo:rustc-link-lib=gcc_pic"); + } else if target.contains("windows-gnu") { + println!("cargo:rustc-link-lib=gcc_eh"); + } else if target.contains("fuchsia") { + println!("cargo:rustc-link-lib=unwind"); + } +} \ No newline at end of file diff --git a/firmware/libunwind-rs/lib.rs b/firmware/libunwind-rs/lib.rs new file mode 100755 index 0000000..2000e5b --- /dev/null +++ b/firmware/libunwind-rs/lib.rs @@ -0,0 +1,29 @@ +// Copyright 2016 The Rust Project Developers. See the COPYRIGHT +// file at the top-level directory of this distribution and at +// http://rust-lang.org/COPYRIGHT. +// +// Licensed under the Apache License, Version 2.0 or the MIT license +// , at your +// option. This file may not be copied, modified, or distributed +// except according to those terms. + +#![no_std] +#![crate_name = "unwind"] +#![crate_type = "rlib"] +#![unstable(feature = "panic_unwind", issue = "32837")] +#![deny(warnings)] + +#![feature(cfg_target_vendor)] +#![feature(staged_api)] +#![feature(unwind_attributes)] + +#![cfg_attr(not(target_env = "msvc"), feature(libc))] + +#[cfg(not(target_env = "msvc"))] +extern crate libc; + +#[cfg(not(target_env = "msvc"))] +mod libunwind; +#[cfg(not(target_env = "msvc"))] +pub use libunwind::*; \ No newline at end of file diff --git a/firmware/libunwind-rs/libunwind.rs b/firmware/libunwind-rs/libunwind.rs new file mode 100755 index 0000000..f230a77 --- /dev/null +++ b/firmware/libunwind-rs/libunwind.rs @@ -0,0 +1,273 @@ +// Copyright 2016 The Rust Project Developers. See the COPYRIGHT +// file at the top-level directory of this distribution and at +// http://rust-lang.org/COPYRIGHT. +// +// Licensed under the Apache License, Version 2.0 or the MIT license +// , at your +// option. This file may not be copied, modified, or distributed +// except according to those terms. + +#![allow(bad_style)] + +macro_rules! cfg_if { + ( $( if #[cfg( $meta:meta )] { $($it1:item)* } else { $($it2:item)* } )* ) => + ( $( $( #[cfg($meta)] $it1)* $( #[cfg(not($meta))] $it2)* )* ) +} + +use libc::{c_int, c_void, uintptr_t}; + +#[repr(C)] +#[derive(Copy, Clone, PartialEq)] +pub enum _Unwind_Reason_Code { + _URC_NO_REASON = 0, + _URC_FOREIGN_EXCEPTION_CAUGHT = 1, + _URC_FATAL_PHASE2_ERROR = 2, + _URC_FATAL_PHASE1_ERROR = 3, + _URC_NORMAL_STOP = 4, + _URC_END_OF_STACK = 5, + _URC_HANDLER_FOUND = 6, + _URC_INSTALL_CONTEXT = 7, + _URC_CONTINUE_UNWIND = 8, + _URC_FAILURE = 9, // used only by ARM EHABI +} +pub use self::_Unwind_Reason_Code::*; + +pub type _Unwind_Exception_Class = u64; +pub type _Unwind_Word = uintptr_t; +pub type _Unwind_Ptr = uintptr_t; +pub type _Unwind_Trace_Fn = extern "C" fn(ctx: *mut _Unwind_Context, arg: *mut c_void) + -> _Unwind_Reason_Code; +#[cfg(target_arch = "x86")] +pub const unwinder_private_data_size: usize = 5; + +#[cfg(target_arch = "x86_64")] +pub const unwinder_private_data_size: usize = 6; + +#[cfg(all(target_arch = "arm", not(target_os = "ios")))] +pub const unwinder_private_data_size: usize = 20; + +#[cfg(all(target_arch = "arm", target_os = "ios"))] +pub const unwinder_private_data_size: usize = 5; + +#[cfg(target_arch = "aarch64")] +pub const unwinder_private_data_size: usize = 2; + +#[cfg(target_arch = "mips")] +pub const unwinder_private_data_size: usize = 2; + +#[cfg(target_arch = "mips64")] +pub const unwinder_private_data_size: usize = 2; + +#[cfg(any(target_arch = "powerpc", target_arch = "powerpc64"))] +pub const unwinder_private_data_size: usize = 2; + +#[cfg(target_arch = "s390x")] +pub const unwinder_private_data_size: usize = 2; + +#[cfg(target_arch = "sparc64")] +pub const unwinder_private_data_size: usize = 2; + +#[cfg(target_os = "emscripten")] +pub const unwinder_private_data_size: usize = 20; + +#[repr(C)] +pub struct _Unwind_Exception { + pub exception_class: _Unwind_Exception_Class, + pub exception_cleanup: _Unwind_Exception_Cleanup_Fn, + pub private: [_Unwind_Word; unwinder_private_data_size], +} + +pub enum _Unwind_Context {} + +pub type _Unwind_Exception_Cleanup_Fn = extern "C" fn(unwind_code: _Unwind_Reason_Code, + exception: *mut _Unwind_Exception); +extern "C" { + #[unwind] + pub fn _Unwind_Resume(exception: *mut _Unwind_Exception) -> !; + pub fn _Unwind_DeleteException(exception: *mut _Unwind_Exception); + pub fn _Unwind_GetLanguageSpecificData(ctx: *mut _Unwind_Context) -> *mut c_void; + pub fn _Unwind_GetRegionStart(ctx: *mut _Unwind_Context) -> _Unwind_Ptr; + pub fn _Unwind_GetTextRelBase(ctx: *mut _Unwind_Context) -> _Unwind_Ptr; + pub fn _Unwind_GetDataRelBase(ctx: *mut _Unwind_Context) -> _Unwind_Ptr; +} + +cfg_if! { +if #[cfg(not(any(all(target_os = "android", target_arch = "arm"), + all(target_os = "linux", target_arch = "arm"))))] { + // Not ARM EHABI + #[repr(C)] + #[derive(Copy, Clone, PartialEq)] + pub enum _Unwind_Action { + _UA_SEARCH_PHASE = 1, + _UA_CLEANUP_PHASE = 2, + _UA_HANDLER_FRAME = 4, + _UA_FORCE_UNWIND = 8, + _UA_END_OF_STACK = 16, + } + pub use self::_Unwind_Action::*; + + extern "C" { + pub fn _Unwind_GetGR(ctx: *mut _Unwind_Context, reg_index: c_int) -> _Unwind_Word; + pub fn _Unwind_SetGR(ctx: *mut _Unwind_Context, reg_index: c_int, value: _Unwind_Word); + pub fn _Unwind_GetIP(ctx: *mut _Unwind_Context) -> _Unwind_Word; + pub fn _Unwind_SetIP(ctx: *mut _Unwind_Context, value: _Unwind_Word); + pub fn _Unwind_GetIPInfo(ctx: *mut _Unwind_Context, ip_before_insn: *mut c_int) + -> _Unwind_Word; + pub fn _Unwind_FindEnclosingFunction(pc: *mut c_void) -> *mut c_void; + } + +} else { + // ARM EHABI + #[repr(C)] + #[derive(Copy, Clone, PartialEq)] + pub enum _Unwind_State { + _US_VIRTUAL_UNWIND_FRAME = 0, + _US_UNWIND_FRAME_STARTING = 1, + _US_UNWIND_FRAME_RESUME = 2, + _US_ACTION_MASK = 3, + _US_FORCE_UNWIND = 8, + _US_END_OF_STACK = 16, + } + pub use self::_Unwind_State::*; + + #[repr(C)] + enum _Unwind_VRS_Result { + _UVRSR_OK = 0, + _UVRSR_NOT_IMPLEMENTED = 1, + _UVRSR_FAILED = 2, + } + #[repr(C)] + enum _Unwind_VRS_RegClass { + _UVRSC_CORE = 0, + _UVRSC_VFP = 1, + _UVRSC_FPA = 2, + _UVRSC_WMMXD = 3, + _UVRSC_WMMXC = 4, + } + use self::_Unwind_VRS_RegClass::*; + #[repr(C)] + enum _Unwind_VRS_DataRepresentation { + _UVRSD_UINT32 = 0, + _UVRSD_VFPX = 1, + _UVRSD_FPAX = 2, + _UVRSD_UINT64 = 3, + _UVRSD_FLOAT = 4, + _UVRSD_DOUBLE = 5, + } + use self::_Unwind_VRS_DataRepresentation::*; + + pub const UNWIND_POINTER_REG: c_int = 12; + pub const UNWIND_IP_REG: c_int = 15; + + extern "C" { + fn _Unwind_VRS_Get(ctx: *mut _Unwind_Context, + regclass: _Unwind_VRS_RegClass, + regno: _Unwind_Word, + repr: _Unwind_VRS_DataRepresentation, + data: *mut c_void) + -> _Unwind_VRS_Result; + + fn _Unwind_VRS_Set(ctx: *mut _Unwind_Context, + regclass: _Unwind_VRS_RegClass, + regno: _Unwind_Word, + repr: _Unwind_VRS_DataRepresentation, + data: *mut c_void) + -> _Unwind_VRS_Result; + } + + // On Android or ARM/Linux, these are implemented as macros: + + pub unsafe fn _Unwind_GetGR(ctx: *mut _Unwind_Context, reg_index: c_int) -> _Unwind_Word { + let mut val: _Unwind_Word = 0; + _Unwind_VRS_Get(ctx, _UVRSC_CORE, reg_index as _Unwind_Word, _UVRSD_UINT32, + &mut val as *mut _ as *mut c_void); + val + } + + pub unsafe fn _Unwind_SetGR(ctx: *mut _Unwind_Context, reg_index: c_int, value: _Unwind_Word) { + let mut value = value; + _Unwind_VRS_Set(ctx, _UVRSC_CORE, reg_index as _Unwind_Word, _UVRSD_UINT32, + &mut value as *mut _ as *mut c_void); + } + + pub unsafe fn _Unwind_GetIP(ctx: *mut _Unwind_Context) + -> _Unwind_Word { + let val = _Unwind_GetGR(ctx, UNWIND_IP_REG); + (val & !1) as _Unwind_Word + } + + pub unsafe fn _Unwind_SetIP(ctx: *mut _Unwind_Context, + value: _Unwind_Word) { + // Propagate thumb bit to instruction pointer + let thumb_state = _Unwind_GetGR(ctx, UNWIND_IP_REG) & 1; + let value = value | thumb_state; + _Unwind_SetGR(ctx, UNWIND_IP_REG, value); + } + + pub unsafe fn _Unwind_GetIPInfo(ctx: *mut _Unwind_Context, + ip_before_insn: *mut c_int) + -> _Unwind_Word { + *ip_before_insn = 0; + _Unwind_GetIP(ctx) + } + + // This function also doesn't exist on Android or ARM/Linux, so make it a no-op + pub unsafe fn _Unwind_FindEnclosingFunction(pc: *mut c_void) -> *mut c_void { + pc + } +} + +if #[cfg(not(all(target_os = "ios", target_arch = "arm")))] { + // Not 32-bit iOS + extern "C" { + #[unwind] + pub fn _Unwind_RaiseException(exception: *mut _Unwind_Exception) -> _Unwind_Reason_Code; + pub fn _Unwind_Backtrace(trace: _Unwind_Trace_Fn, + trace_argument: *mut c_void) + -> _Unwind_Reason_Code; + } +} else { + // 32-bit iOS uses SjLj and does not provide _Unwind_Backtrace() + extern "C" { + #[unwind] + pub fn _Unwind_SjLj_RaiseException(e: *mut _Unwind_Exception) -> _Unwind_Reason_Code; + } + + #[inline] + pub unsafe fn _Unwind_RaiseException(exc: *mut _Unwind_Exception) -> _Unwind_Reason_Code { + _Unwind_SjLj_RaiseException(exc) + } +} +} // cfg_if! + +#[cfg_attr(any(all(target_os = "linux", not(target_env = "musl")), + target_os = "freebsd", + target_os = "solaris", + target_os = "haiku", + all(target_os = "linux", + target_env = "musl", + not(target_arch = "x86"), + not(target_arch = "x86_64"))), + link(name = "gcc_s"))] +#[cfg_attr(all(target_os = "linux", + target_env = "musl", + any(target_arch = "x86", target_arch = "x86_64"), + not(test)), + link(name = "unwind", kind = "static"))] +#[cfg_attr(target_os = "fuchsia", + link(name = "unwind"))] +#[cfg_attr(any(target_os = "android", target_os = "openbsd"), + link(name = "gcc"))] +#[cfg_attr(all(target_os = "netbsd", not(target_vendor = "rumprun")), + link(name = "gcc"))] +#[cfg_attr(all(target_os = "netbsd", target_vendor = "rumprun"), + link(name = "unwind"))] +#[cfg_attr(target_os = "dragonfly", + link(name = "gcc_pic"))] +#[cfg_attr(target_os = "bitrig", + link(name = "c++abi"))] +#[cfg_attr(all(target_os = "windows", target_env = "gnu"), + link(name = "gcc_eh"))] +#[cfg(not(cargobuild))] +extern "C" {} \ No newline at end of file diff --git a/firmware/runtime/Cargo.toml b/firmware/runtime/Cargo.toml new file mode 100755 index 0000000..19e5569 --- /dev/null +++ b/firmware/runtime/Cargo.toml @@ -0,0 +1,20 @@ +[package] +name = "runtime" +version = "0.1.0" +authors = ["cjb "] + + +[build-dependencies] +cc = "1.0" + + +[dependencies] +board_misoc = { path = "../libboard_misoc"} +ksupport = { path = "../libksupport"} +volatile_cell = "*" + + +[lib] +path="main.rs" +name = "runtime" +crate-type = ["staticlib"] diff --git a/firmware/runtime/Makefile b/firmware/runtime/Makefile new file mode 100755 index 0000000..7b7bb62 --- /dev/null +++ b/firmware/runtime/Makefile @@ -0,0 +1,27 @@ +include ../include/generated/variables.mak +include $(MISOC_DIRECTORY)/software/common.mak + + +LDFLAGS += --eh-frame-hdr \ + -L../libm \ + -L../libprintf \ + -L../libunwind \ + --start-group + +RUSTFLAGS += -Cpanic=unwind + + +all:: runtime.bin + +.PHONY: $(RUSTOUT)/libruntime.a +$(RUSTOUT)/libruntime.a: + $(cargo) --manifest-path $(RUNTIME_DIRECTORY)/Cargo.toml + +runtime.elf: $(RUSTOUT)/libruntime.a $(RUNTIME_DIRECTORY)/exp.a ../libunwind/libunwind-bare.a + $(link) -T $(RUNTIME_DIRECTORY)/lscript.ld -lprintf-float -lm $(BUILDINC_DIRECTORY)/../libbase/libbase.a -lunwind-bare --target2=abs + +%.bin: %.elf + $(objcopy) -O binary -R .uncachable + +%.o: $(RUNTIME_DIRECTORY)/%.c + $(compile) diff --git a/firmware/runtime/build.rs b/firmware/runtime/build.rs new file mode 100755 index 0000000..0425f4e --- /dev/null +++ b/firmware/runtime/build.rs @@ -0,0 +1,17 @@ +extern crate cc; + + +fn main() { + let startup_path = "startup.S"; + let table_path = "translation_table.S"; + + println!("cargo:rerun-if-changed={}", startup_path); + println!("cargo:rerun-if-changed={}", table_path); + + cc::Build::new() + .file(startup_path) + .compile("startup"); + cc::Build::new() + .file(table_path) + .compile("translation_table"); +} diff --git a/firmware/runtime/glue.c b/firmware/runtime/glue.c new file mode 100755 index 0000000..b48d0bd --- /dev/null +++ b/firmware/runtime/glue.c @@ -0,0 +1,68 @@ +#include +#include +#include +#include +#include + +struct slice { + void *ptr; + size_t len; +}; + +void send_to_core_log(struct slice str); + +#define KERNELCPU_EXEC_ADDRESS 0x40800000 +#define KERNELCPU_PAYLOAD_ADDRESS 0x40840000 +#define KERNELCPU_LAST_ADDRESS 0x4fffffff +#define KSUPPORT_HEADER_SIZE 0x80 + + +/* called by kernel */ +double round(double x); +double round(double x) +{ + union {double f; uint64_t i;} u = {x}; + int e = u.i >> 52 & 0x7ff; + double y; + + if (e >= 0x3ff+52) + return x; + if (u.i >> 63) + x = -x; + if (e < 0x3ff-1) { + /* we don't do it in ARTIQ */ + /* raise inexact if x!=0 */ + // FORCE_EVAL(x + 0x1p52); + return 0*u.f; + } + y = (double)(x + 0x1p52) - 0x1p52 - x; + if (y > 0.5) + y = y + x - 1; + else if (y <= -0.5) + y = y + x + 1; + else + y = y + x; + if (u.i >> 63) + y = -y; + return y; +} + +/* called by kernel */ +int core_log(const char *fmt, ...); +int core_log(const char *fmt, ...) +{ + va_list args; + + va_start(args, fmt); + size_t size = vsnprintf(NULL, 0, fmt, args); + char *buf = __builtin_alloca(size + 1); + va_end(args); + + va_start(args, fmt); + vsnprintf(buf, size + 1, fmt, args); + va_end(args); + + struct slice str = { buf, size }; + send_to_core_log(str); + return 0; +} diff --git a/firmware/runtime/lscript.ld b/firmware/runtime/lscript.ld new file mode 100755 index 0000000..18e0897 --- /dev/null +++ b/firmware/runtime/lscript.ld @@ -0,0 +1,83 @@ + +ENTRY(_boot) + +MEMORY { + runtime (RWX) : ORIGIN = 0x100000, LENGTH = 0x1FF00000 +} + +SECTIONS +{ + .text : + { + *(.vectors) + *(.text .text.*) + } > runtime + + .ARM.extab : { + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + } > runtime + + .ARM.exidx : { + __exidx_start = .; + *(.ARM.exidx*) + *(.gnu.linkonce.armexidix.*.*) + __exidx_end = .; + } > runtime + + /* https://sourceware.org/bugzilla/show_bug.cgi?id=20475 */ + .got : + { + _GLOBAL_OFFSET_TABLE_ = .; + *(.got) + } > runtime + + .got.plt : + { + *(.got.plt) + } > runtime + + .rodata ALIGN(4): + { + *(.rodata .rodata.*) + } > runtime + + .data ALIGN(4): + { + *(.data .data.*) + } > runtime + + .bss ALIGN(4) : + { + _fbss = .; + *(.bss .bss.*) + _ebss = .; + } > runtime + + .stack ALIGN(0x1000) : + { + . += 0x4000; + _fstack = . - 4; + } > runtime + + .stack2 ALIGN(0x1000) : + { + . += 0x4000; + _fstack2 = . - 4; + } > runtime + + .mmu_tbl (ALIGN(16384)) : + { + __mmu_tbl_start = .; + *(.mmu_tbl) + __mmu_tbl_end = .; + } > runtime + + + .uncachable ALIGN(0x100000) : + { + __uncachable_start = .; + *(.uncachable) + __uncachable_end = .; + } > runtime +} diff --git a/firmware/runtime/main.rs b/firmware/runtime/main.rs new file mode 100755 index 0000000..6d57140 --- /dev/null +++ b/firmware/runtime/main.rs @@ -0,0 +1,92 @@ +#![no_std] +#![feature(panic_implementation, lang_items, asm)] +#[allow(unused_imports)] + +#[macro_use] +extern crate board_misoc; +extern crate ksupport; + +extern { + // Statically linked python module entry point + fn __modinit__(); +} + + +#[inline(never)] +pub fn get_cycle_counter() -> u32 { + let n: u32; + unsafe{asm!("mrc p15, 0, $0, c9, c13, 0": "=r"(n) ::: "volatile");} + n +} + + +use board_misoc::csr; +unsafe fn crg_init() { + csr::rtio_crg::pll_reset_write(1); + csr::rtio_crg::pll_reset_write(0); + + println!("Waiting on PLL lock ... "); + while csr::rtio_crg::pll_locked_read() == 0 {} + println!("PLL locked.\n"); +} + + +#[no_mangle] +pub extern "C" fn main() -> ! { + println!(""); + println!(""); + println!("-----------------"); + println!("Artiq-Zynq lashup"); + + unsafe{ + csr::dma::addr_base_write(0x200000 as u32); + csr::cri_con::selected_write(1); + crg_init(); + } + + + println!("Starting kernel..."); + println!("--"); + unsafe{ __modinit__() } + println!("--"); + println!("Kernel finished"); + + loop {} +} + + + +#[no_mangle] +pub extern "C" fn data_abort_handler(abort_addr: u32, access_addr: u32, data_fault_status: u32) -> ! { + println!("!!! Data abort"); + println!("PC = {:08x}", abort_addr-0x8); + println!("Access addr = {:08x}", access_addr); + println!("DFSR = {:08x}", data_fault_status); + loop {} +} + +#[no_mangle] +pub extern "C" fn undefined_instruction_handler(abort_addr: u32) -> ! { + println!("!!! Undefined instruction"); + println!("PC = {:08x}", abort_addr-0x4); + loop {} +} + +#[no_mangle] +pub extern "C" fn irq_handler() -> ! { + println!("!!! IRQ"); + loop {} +} + +#[no_mangle] +#[lang = "eh_personality"] pub extern fn eh_personality() {} + +use core::panic::PanicInfo; + +// This function is called on panic (including failed assertions, ...). +#[panic_implementation] +#[no_mangle] +pub fn panic(info: &PanicInfo) -> ! { + println!("kernel {}", info); + loop {} +} diff --git a/firmware/runtime/startup.S b/firmware/runtime/startup.S new file mode 100755 index 0000000..4c88240 --- /dev/null +++ b/firmware/runtime/startup.S @@ -0,0 +1,320 @@ +.global _boot +.global _start +.global data_abort_handler + +.global _vector_table +.global MMUTable + +.set vector_base, _vector_table + +.set TblBase, MMUTable +.set UncachableStart, __uncachable_start +.set UncachableEnd, __uncachable_end +.set CRValMmuCac, 0b01000000000101 /* Enable IDC, and MMU */ + +.set PSS_SLCR_BASE_ADDR, 0xF8000000 +.set PSS_L2CC_BASE_ADDR, 0xF8F02000 + +.set L2CCWay, (PSS_L2CC_BASE_ADDR + 0x077C) /*(PSS_L2CC_BASE_ADDR + PSS_L2CC_CACHE_INVLD_WAY_OFFSET)*/ +.set L2CCSync, (PSS_L2CC_BASE_ADDR + 0x0730) /*(PSS_L2CC_BASE_ADDR + PSS_L2CC_CACHE_SYNC_OFFSET)*/ +.set L2CCCrtl, (PSS_L2CC_BASE_ADDR + 0x0100) /*(PSS_L2CC_BASE_ADDR + PSS_L2CC_CNTRL_OFFSET)*/ +.set L2CCAuxCrtl, (PSS_L2CC_BASE_ADDR + 0x0104) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_AUX_CNTRL_OFFSET)*/ +.set L2CCTAGLatReg, (PSS_L2CC_BASE_ADDR + 0x0108) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_TAG_RAM_CNTRL_OFFSET)*/ +.set L2CCDataLatReg, (PSS_L2CC_BASE_ADDR + 0x010C) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_DATA_RAM_CNTRL_OFFSET)*/ +.set L2CCIntClear, (PSS_L2CC_BASE_ADDR + 0x0220) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_IAR_OFFSET)*/ +.set L2CCIntRaw, (PSS_L2CC_BASE_ADDR + 0x021C) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_ISR_OFFSET)*/ +.set L2CCAuxControl, 0x72360000 /* Enable all prefetching, Cache replacement policy, Parity enable, + Event monitor bus enable and Way Size (64 KB) */ +.set L2CCControl, 0x01 /* Enable L2CC */ +.set L2CCTAGLatency, 0x0111 /* latency for TAG RAM */ +.set L2CCDataLatency, 0x0121 /* latency for DATA RAM */ +.set SLCRlockReg, (PSS_SLCR_BASE_ADDR + 0x04) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_LOCK_OFFSET)*/ +.set SLCRUnlockReg, (PSS_SLCR_BASE_ADDR + 0x08) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_UNLOCK_OFFSET)*/ +.set SLCRL2cRamReg, (PSS_SLCR_BASE_ADDR + 0xA1C) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_L2C_RAM_OFFSET)*/ +.set SLCRlockKey, 0x767B /* SLCR lock key */ +.set SLCRUnlockKey, 0xDF0D /* SLCR unlock key */ +.set SLCRL2cRamConfig, 0x00020202 /* SLCR L2C ram configuration */ + + +.org 0 +.text + +.globl _vector_table + +.section .vectors +_vector_table: + B _boot + B Undefined + B SVCHandler + B PrefetchAbortHandler + B DataAbortHandler + NOP /* Placeholder for address exception vector*/ + B IRQHandler + B FIQHandler + + +.text + +_boot: + // Read MPIDR to determine processor id + mrc p15,0,r0,c0,c0,5 + and r0, r0, 0x3 + cmp r0, 0 + // processor 0 -> p0_boot + // processor 1 waits for interrupt, then goes via p1_boot + beq p0_start + ldr r13,.Lstack2 /* stack address */ +p1_loop: + wfi + b p1_loop +p0_start: + + /* set VBAR to the _vector_table address in linker script */ + ldr r0, =vector_base + mcr p15, 0, r0, c12, c0, 0 + + /*invalidate scu*/ + ldr r7, =0xf8f0000c + ldr r6, =0xffff + str r6, [r7] + + /* Invalidate caches and TLBs */ + mov r0,#0 /* r0 = 0 */ + mcr p15, 0, r0, c8, c7, 0 /* invalidate TLBs */ + mcr p15, 0, r0, c7, c5, 0 /* invalidate icache */ + mcr p15, 0, r0, c7, c5, 6 /* Invalidate branch predictor array */ + bl invalidate_dcache /* invalidate dcache */ + + /* Disable MMU, if enabled */ + mrc p15, 0, r0, c1, c0, 0 /* read CP15 register 1 */ + bic r0, r0, #0x1 /* clear bit 0 */ + mcr p15, 0, r0, c1, c0, 0 /* write value back */ + + /* Mark the a section of DDR as uncacheable */ + ldr r3, =UncachableStart + ldr r4, =UncachableEnd + ldr r0, =TblBase /* MMU Table address in memory */ + ldr r2, =0x11de2 /* S=b1 TEX=b001 AP=b11, Domain=b1111, C=b0, B=b0 */ + lsr r5, r3, #18 // Calculate table offset + add r0, r0, r5 // Address of first table entry to modify +uncacheable_loop: + add r5, r3, r2 + str r5, [r0] // write the entry to MMU table + add r0, r0, #0x4 // next entry in the table + add r3, r3, #0x100000 // next section + cmp r3, r4 + blt uncacheable_loop + + /*set scu enable bit in scu*/ + ldr r7, =0xf8f00000 + ldr r0, [r7] + orr r0, r0, #0x1 + str r0, [r7] + + // enable MMU and cache + ldr r0,=TblBase /* Load MMU translation table base */ + orr r0, r0, #0x5B /* Outer-cacheable, WB */ + mcr p15, 0, r0, c2, c0, 0 /* TTB0 */ + + mvn r0,#0 /* Load MMU domains -- all ones=manager */ + mcr p15,0,r0,c3,c0,0 + + // Enable mmu, icache and dcache + ldr r0,=CRValMmuCac + mcr p15,0,r0,c1,c0,0 /* Enable cache and MMU */ + dsb /* dsb allow the MMU to start up */ + isb /* isb flush prefetch buffer */ + + /* Write to ACTLR */ + mrc p15, 0, r0, c1, c0, 1 /* Read ACTLR*/ + orr r0, r0, #(0x01 << 6) /* set SMP bit */ + orr r0, r0, #(0x01 ) /* Cache/TLB maintenance broadcast */ + mcr p15, 0, r0, c1, c0, 1 /* Write ACTLR*/ + +/* Invalidate L2 Cache and enable L2 Cache*/ + ldr r0,=L2CCCrtl /* Load L2CC base address base + control register */ + mov r1, #0 /* force the disable bit */ + str r1, [r0] /* disable the L2 Caches */ + + ldr r0,=L2CCAuxCrtl /* Load L2CC base address base + Aux control register */ + ldr r1,[r0] /* read the register */ + ldr r2,=L2CCAuxControl /* set the default bits */ + orr r1,r1,r2 + str r1, [r0] /* store the Aux Control Register */ + + ldr r0,=L2CCTAGLatReg /* Load L2CC base address base + TAG Latency address */ + ldr r1,=L2CCTAGLatency /* set the latencies for the TAG*/ + str r1, [r0] /* store the TAG Latency register Register */ + + ldr r0,=L2CCDataLatReg /* Load L2CC base address base + Data Latency address */ + ldr r1,=L2CCDataLatency /* set the latencies for the Data*/ + str r1, [r0] /* store the Data Latency register Register */ + + ldr r0,=L2CCWay /* Load L2CC base address base + way register*/ + ldr r2, =0xFFFF + str r2, [r0] /* force invalidate */ + + ldr r0,=L2CCSync /* need to poll 0x730, PSS_L2CC_CACHE_SYNC_OFFSET */ + /* Load L2CC base address base + sync register*/ + /* poll for completion */ +Sync: ldr r1, [r0] + cmp r1, #0 + bne Sync + + ldr r0,=L2CCIntRaw /* clear pending interrupts */ + ldr r1,[r0] + ldr r0,=L2CCIntClear + str r1,[r0] + + ldr r0,=SLCRUnlockReg /* Load SLCR base address base + unlock register */ + ldr r1,=SLCRUnlockKey /* set unlock key */ + str r1, [r0] /* Unlock SLCR */ + + ldr r0,=SLCRL2cRamReg /* Load SLCR base address base + l2c Ram Control register */ + ldr r1,=SLCRL2cRamConfig /* set the configuration value */ + str r1, [r0] /* store the L2c Ram Control Register */ + + ldr r0,=SLCRlockReg /* Load SLCR base address base + lock register */ + ldr r1,=SLCRlockKey /* set lock key */ + str r1, [r0] /* lock SLCR */ + + ldr r0,=L2CCCrtl /* Load L2CC base address base + control register */ + ldr r1,[r0] /* read the register */ + mov r2, #L2CCControl /* set the enable bit */ + orr r1,r1,r2 + str r1, [r0] /* enable the L2 Caches */ + mov r0,r0 + + // Enable CP11 and CP10 access from all processor modes + mrc p15, 0, r0, c1, c0, 2 // Read CPACR + orr r0, r0, (0b1111<<20) + mcr p15, 0, r0, c1, c0, 2 + + /* enable vfp */ + vmrs r1, fpexc + orr r1,r1, (1<<30) + vmsr fpexc, r1 + + mrc p15,0,r0,c1,c0,0 /* flow prediction enable */ + orr r0, r0, #(0x01 << 11) /* #0x8000 */ + mcr p15,0,r0,c1,c0,0 + + mrc p15,0,r0,c1,c0,1 /* read Auxiliary Control Register */ + orr r0, r0, #(0x1 << 2) /* enable Dside prefetch */ + orr r0, r0, #(0x1 << 1) /* enable L2 Prefetch hint */ + mcr p15,0,r0,c1,c0,1 /* write Auxiliary Control Register */ + + mrs r0, cpsr /* get the current PSR */ + bic r0, r0, #0x100 /* enable asynchronous abort exception */ + msr cpsr_xsf, r0 + + + // Enable and reset cycle counter + mov r0, 0b101 + mcr p15, 0, r0, c9, c12, 0 + + +.Lenclsbss: + /* clear bss */ + ldr r1,.Lbss_start /* calculate beginning of the BSS */ + ldr r2,.Lbss_end /* calculate end of the BSS */ + +.Lloop_bss: + cmp r1,r2 + bge .Lenclbss /* If no BSS, no clearing required */ + str r0, [r1], #4 + b .Lloop_bss + +.Lenclbss: + /* set stack pointer */ + ldr r13,.Lstack /* stack address */ + + + bl main +loop: + b loop + + +Undefined: + ldr r13, .Lstack + mov r0, lr // address of undefined instruction +8 + b undefined_instruction_handler + +SVCHandler: + b SVCHandler + +PrefetchAbortHandler: + b PrefetchAbortHandler + +DataAbortHandler: + ldr r13, .Lstack + mov r0, lr // address of aborted instruction +8 + mrc p15, 0, r1, c6, c0, 0 // Read DFAR + mrc p15, 0, r2, c5, c0, 0 // Read DFSR + b data_abort_handler + +IRQHandler: + ldr r13, .Lstack + b irq_handler + +FIQHandler: + b FIQHandler + +invalidate_dcache: + mrc p15, 1, r0, c0, c0, 1 /* read CLIDR */ + ands r3, r0, #0x7000000 + mov r3, r3, lsr #23 /* cache level value (naturally aligned) */ + beq finished + mov r10, #0 /* start with level 0 */ +loop1: + add r2, r10, r10, lsr #1 /* work out 3xcachelevel */ + mov r1, r0, lsr r2 /* bottom 3 bits are the Cache type for this level */ + and r1, r1, #7 /* get those 3 bits alone */ + cmp r1, #2 + blt skip /* no cache or only instruction cache at this level */ + mcr p15, 2, r10, c0, c0, 0 /* write the Cache Size selection register */ + isb /* isb to sync the change to the CacheSizeID reg */ + mrc p15, 1, r1, c0, c0, 0 /* reads current Cache Size ID register */ + and r2, r1, #7 /* extract the line length field */ + add r2, r2, #4 /* add 4 for the line length offset (log2 16 bytes) */ + ldr r4, =0x3ff + ands r4, r4, r1, lsr #3 /* r4 is the max number on the way size (right aligned) */ + clz r5, r4 /* r5 is the bit position of the way size increment */ + ldr r7, =0x7fff + ands r7, r7, r1, lsr #13 /* r7 is the max number of the index size (right aligned) */ +loop2: + mov r9, r4 /* r9 working copy of the max way size (right aligned) */ +loop3: + orr r11, r10, r9, lsl r5 /* factor in the way number and cache number into r11 */ + orr r11, r11, r7, lsl r2 /* factor in the index number */ + mcr p15, 0, r11, c7, c6, 2 /* invalidate by set/way */ + subs r9, r9, #1 /* decrement the way number */ + bge loop3 + subs r7, r7, #1 /* decrement the index */ + bge loop2 +skip: + add r10, r10, #2 /* increment the cache number */ + cmp r3, r10 + bgt loop1 + +finished: + mov r10, #0 /* swith back to cache level 0 */ + mcr p15, 2, r10, c0, c0, 0 /* select current cache level in cssr */ + dsb + isb + + bx lr + + + +.Lbss_start: + .long _fbss + +.Lbss_end: + .long _ebss + +.Lstack: + .long _fstack + +.Lstack2: + .long _fstack2 \ No newline at end of file diff --git a/firmware/runtime/translation_table.S b/firmware/runtime/translation_table.S new file mode 100755 index 0000000..6320103 --- /dev/null +++ b/firmware/runtime/translation_table.S @@ -0,0 +1,185 @@ +/*****************************************************************************/ +/** +* @file translation_table.s +* +* @addtogroup a9_boot_code +* @{ +*

translation_table.S

+* translation_table.S contains a static page table required by MMU for +* cortex-A9. This translation table is flat mapped (input address = output +* address) with default memory attributes defined for zynq architecture. It +* utilizes short descriptor translation table format with each section defining +* 1MB of memory. +* +* The overview of translation table memory attributes is described below. +* +*| | Memory Range | Definition in Translation Table | +*|-----------------------|-------------------------|-----------------------------------| +*| DDR | 0x00000000 - 0x3FFFFFFF | Normal write-back Cacheable | +*| PL | 0x40000000 - 0xBFFFFFFF | Strongly Ordered | +*| Reserved | 0xC0000000 - 0xDFFFFFFF | Unassigned | +*| Memory mapped devices | 0xE0000000 - 0xE02FFFFF | Device Memory | +*| Reserved | 0xE0300000 - 0xE0FFFFFF | Unassigned | +*| NAND, NOR | 0xE1000000 - 0xE3FFFFFF | Device memory | +*| SRAM | 0xE4000000 - 0xE5FFFFFF | Normal write-back Cacheable | +*| Reserved | 0xE6000000 - 0xF7FFFFFF | Unassigned | +*| AMBA APB Peripherals | 0xF8000000 - 0xF8FFFFFF | Device Memory | +*| Reserved | 0xF9000000 - 0xFBFFFFFF | Unassigned | +*| Linear QSPI - XIP | 0xFC000000 - 0xFDFFFFFF | Normal write-through cacheable | +*| Reserved | 0xFE000000 - 0xFFEFFFFF | Unassigned | +*| OCM | 0xFFF00000 - 0xFFFFFFFF | Normal inner write-back cacheable | +* +* @note +* +* For region 0x00000000 - 0x3FFFFFFF, a system where DDR is less than 1GB, +* region after DDR and before PL is marked as undefined/reserved in translation +* table. In 0xF8000000 - 0xF8FFFFFF, 0xF8000C00 - 0xF8000FFF, 0xF8010000 - +* 0xF88FFFFF and 0xF8F03000 to 0xF8FFFFFF are reserved but due to granual size +* of 1MB, it is not possible to define separate regions for them. For region +* 0xFFF00000 - 0xFFFFFFFF, 0xFFF00000 to 0xFFFB0000 is reserved but due to 1MB +* granual size, it is not possible to define separate region for it +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a ecm  10/20/09 Initial version
+* 3.04a sdm  01/13/12 Updated MMU table to mark DDR memory as Shareable
+* 3.07a sgd  07/05/2012 Configuring device address spaces as shareable device
+*              instead of strongly-ordered.
+* 3.07a asa  07/17/2012 Changed the property of the ".mmu_tbl" section.
+* 4.2   pkp  09/02/2014 added entries for 0xfe000000 to 0xffefffff as reserved
+*           and  0xe0000000 - 0xe1ffffff is broken down into
+*           0xe0000000 - 0xe02fffff (memory mapped devides)
+*           0xe0300000 - 0xe0ffffff (reserved) and
+*           0xe1000000 - 0xe1ffffff (NAND)
+* 5.2   pkp  06/08/2015 put a check for XPAR_PS7_DDR_0_S_AXI_BASEADDR to confirm
+*           if DDR is present or not and accordingly generate the
+*           translation table
+* 6.1   pkp  07/11/2016 Corrected comments for memory attributes
+*
+* +* +******************************************************************************/ + .globl MMUTable + + .section .mmu_tbl,"a" + +MMUTable: + /* Each table entry occupies one 32-bit word and there are + * 4096 entries, so the entire table takes up 16KB. + * Each entry covers a 1MB section. + */ +.set SECT, 0 + +.set DDR_START, 0x00100000 +.set DDR_END, 0x1FFFFFFF +.set DDR_SIZE, (DDR_END - DDR_START)+1 +.set DDR_REG, DDR_SIZE/0x100000 + + +.set UNDEF_REG, 0x3FF - DDR_REG + + /*0x00000000 - 0x00100000 (cacheable )*/ +.word SECT + 0x15de6 /* S=b1 TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1 */ +.set SECT, SECT+0x100000 + +.rept DDR_REG /* (DDR Cacheable) */ +.word SECT + 0x15de6 /* S=b1 TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1 */ +.set SECT, SECT+0x100000 +.endr + +.rept UNDEF_REG /* (unassigned/reserved). + * Generates a translation fault if accessed */ +.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */ +.set SECT, SECT+0x100000 +.endr + + +.rept 0x0400 /* 0x40000000 - 0x7fffffff (FPGA slave0) */ +.word SECT + 0xc02 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b0 */ +.set SECT, SECT+0x100000 +.endr + +.rept 0x0400 /* 0x80000000 - 0xbfffffff (FPGA slave1) */ +.word SECT + 0xc02 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b0 */ +.set SECT, SECT+0x100000 +.endr + +.rept 0x0200 /* 0xc0000000 - 0xdfffffff (unassigned/reserved). + * Generates a translation fault if accessed */ +.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */ +.set SECT, SECT+0x100000 +.endr + +.rept 0x003 /* 0xe0000000 - 0xe02fffff (Memory mapped devices) + * UART/USB/IIC/SPI/CAN/GEM/GPIO/QSPI/SD/NAND */ +.word SECT + 0xc06 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */ +.set SECT, SECT+0x100000 +.endr + +.rept 0x0D /* 0xe0300000 - 0xe0ffffff (unassigned/reserved). + * Generates a translation fault if accessed */ +.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */ +.set SECT, SECT+0x100000 +.endr + +.rept 0x0010 /* 0xe1000000 - 0xe1ffffff (NAND) */ +.word SECT + 0xc06 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */ +.set SECT, SECT+0x100000 +.endr + +.rept 0x0020 /* 0xe2000000 - 0xe3ffffff (NOR) */ +.word SECT + 0xc06 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */ +.set SECT, SECT+0x100000 +.endr + +.rept 0x0020 /* 0xe4000000 - 0xe5ffffff (SRAM) */ +.word SECT + 0xc0e /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b1, B=b1 */ +.set SECT, SECT+0x100000 +.endr + +.rept 0x0120 /* 0xe6000000 - 0xf7ffffff (unassigned/reserved). + * Generates a translation fault if accessed */ +.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */ +.set SECT, SECT+0x100000 +.endr + +/* 0xf8000c00 to 0xf8000fff, 0xf8010000 to 0xf88fffff and + 0xf8f03000 to 0xf8ffffff are reserved but due to granual size of + 1MB, it is not possible to define separate regions for them */ + +.rept 0x0010 /* 0xf8000000 - 0xf8ffffff (AMBA APB Peripherals) */ + +.word SECT + 0xc06 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */ +.set SECT, SECT+0x100000 +.endr + +.rept 0x0030 /* 0xf9000000 - 0xfbffffff (unassigned/reserved). + * Generates a translation fault if accessed */ +.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */ +.set SECT, SECT+0x100000 +.endr + +.rept 0x0020 /* 0xfc000000 - 0xfdffffff (Linear QSPI - XIP) */ +.word SECT + 0xc0a /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b1, B=b0 */ +.set SECT, SECT+0x100000 +.endr + +.rept 0x001F /* 0xfe000000 - 0xffefffff (unassigned/reserved). + * Generates a translation fault if accessed */ +.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */ +.set SECT, SECT+0x100000 +.endr + +/* 0xfff00000 to 0xfffb0000 is reserved but due to granual size of + 1MB, it is not possible to define separate region for it + + 0xfff00000 - 0xffffffff + 256K OCM when mapped to high address space + inner-cacheable */ +.word SECT + 0x4c0e /* S=b0 TEX=b100 AP=b11, Domain=b0, C=b1, B=b1 */ +.set SECT, SECT+0x100000 + +.end diff --git a/hp_dma.py b/hp_dma.py new file mode 100755 index 0000000..1451ee4 --- /dev/null +++ b/hp_dma.py @@ -0,0 +1,106 @@ +from migen import * +from migen_axi.interconnect import axi +from misoc.interconnect.csr import * +from operator import attrgetter + + +class HP_DMA_READ(Module, AutoCSR): + def __init__(self, bus=None): + self.bus = bus or axi.Interface(data_width=64) + + self.addr_base = CSRStorage(32) + self.n_bursts = CSRStorage(32) # Number of bursts to do -1 + self.trigger = CSR(1) + + self.n_cycles = CSRStatus(32) + self.status = CSRStatus(1) + self.n_read = CSRStatus(32) + + self.dout = Signal(32) + self.dout_stb = Signal() + + ### + ar, aw, w, r, b = attrgetter("ar", "aw", "w", "r", "b")(self.bus) + BURST_LEN = 16 + + trigger_stb = self.trigger.re + addr = Signal(32) + read_request_accepted = Signal() # Asserted when the read request has been accepted + read_request = Signal() + n_done = Signal(32) + + self.submodules.fsm = fsm = FSM(reset_state="IDLE") + fsm.act("IDLE", + If(trigger_stb, + NextValue(addr, self.addr_base.storage), + NextValue(read_request, 1), + NextState("RUNNING") + ) + ) + fsm.act("RUNNING", + If(read_request_accepted, + NextValue(addr, addr+BURST_LEN), + NextValue(n_done, n_done+1), + If(n_done == self.n_bursts.storage, + NextState("IDLE"), + NextValue(read_request, 0) + ) + ) + ) + + + ### Read + self.comb += [ + ar.addr.eq(self.addr_base.storage), + self.dout.eq(r.data), + r.ready.eq(1), + ar.burst.eq(axi.Burst.incr.value), + ar.len.eq(BURST_LEN-1), # Number of transfers in burst (0->1 transfer, 1->2 transfers...) + ar.size.eq(3), # Width of burst: 3 = 8 bytes = 64 bits + ar.cache.eq(0xf), + ] + + # read control + self.comb += read_request_accepted.eq(ar.ready & ar.valid) + self.submodules.read_fsm = read_fsm = FSM(reset_state="IDLE") + read_fsm.act("IDLE", + If(read_request, + ar.valid.eq(1), + If(ar.ready, + NextState("WAIT") + ).Else( + NextState("READ_START") + ) + ) + ) + read_fsm.act("READ_START", + ar.valid.eq(1), + If(ar.ready, + NextState("WAIT"), + ) + ) + read_fsm.act("WAIT", + NextState("IDLE") + ) + + self.comb += self.dout_stb.eq(r.valid & r.ready) + + n_bursts_received = Signal(32) + self.sync += [ + If(trigger_stb, n_bursts_received.eq(0)), + If(self.dout_stb & r.last, n_bursts_received.eq(n_bursts_received+1)) + ] + + self.sync += [ + If(trigger_stb, self.status.status.eq(1)), + If(n_bursts_received==self.n_bursts.storage+1, self.status.status.eq(0)) + ] + self.sync += [ + If(self.status.status, self.n_cycles.status.eq(self.n_cycles.status+1)), + If(trigger_stb, self.n_cycles.status.eq(0)) + ] + + self.sync += [ + If(self.dout_stb, self.n_read.status.eq(self.n_read.status+1)), + If(trigger_stb, self.n_read.status.eq(0)) + ] \ No newline at end of file diff --git a/load.py b/load.py new file mode 100755 index 0000000..a33b830 --- /dev/null +++ b/load.py @@ -0,0 +1,90 @@ +#!/usr/bin/env python + +import argparse +import tempfile +import os +import subprocess + + +header_template = \ +""" +source [find interface/ftdi/digilent_jtag_smt2.cfg] +adapter_khz 10000 + +set PL_TAPID 0x03727093 +set SMP 1 + +source {cfg_dir}/zynq-7000.cfg +source {cfg_dir}/xilinx-tcl.cfg +source {cfg_dir}/ps7_init.tcl + +reset_config srst_only srst_push_pull + +set XC7_JSHUTDOWN 0x0d +set XC7_JPROGRAM 0x0b +set XC7_JSTART 0x0c +set XC7_BYPASS 0x3f + +proc xc7_program {{tap}} {{ + global XC7_JSHUTDOWN XC7_JPROGRAM XC7_JSTART XC7_BYPASS + irscan $tap $XC7_JSHUTDOWN + irscan $tap $XC7_JPROGRAM + runtest 60000 + #JSTART prevents this from working... + #irscan $tap $XC7_JSTART + runtest 2000 + irscan $tap $XC7_BYPASS + runtest 2000 +}} + +pld device virtex2 zynq.tap 1 +init +xc7_program zynq.tap + +xilinx_ps7_init + +# Disable MMU +targets $_TARGETNAME_1 +arm mcr 15 0 1 0 0 [expr [arm mrc 15 0 1 0 0] & ~0xd] +targets $_TARGETNAME_0 +arm mcr 15 0 1 0 0 [expr [arm mrc 15 0 1 0 0] & ~0xd] +""" + + +def get_argparser(): + parser = argparse.ArgumentParser() + + parser.add_argument("action", nargs="*", + default="gateware firmware run stop".split()) + return parser + + +def main(): + args = get_argparser().parse_args() + + with tempfile.NamedTemporaryFile(delete=False) as f: + cfg_file = f.name + + cfg_dir = os.path.dirname(os.path.realpath(__file__)) + header = header_template.format(cfg_dir=cfg_dir) + f.write(header.encode()) + + if "firmware" in args.action: + f.write(b"load_image misoc_zedboard_zedboard/software/runtime/runtime.bin 0x100000 bin\n") + if "gateware" in args.action: + f.write(b"pld load 0 misoc_zedboard_zedboard/gateware/top.bit\n") + if "run" in args.action: + f.write(b"targets $_TARGETNAME_1\nreg pc 0x100000\n") + f.write(b"targets $_TARGETNAME_0\nresume 0x100000\n") + if "stop" in args.action: + f.write(b"sleep 2000\n") + f.write(b"targets $_TARGETNAME_0\nhalt\nreg\n") +# f.write(b"targets $_TARGETNAME_1\nhalt\nreg\n") + + if not ("noexit" in args.action): + f.write(b"exit\n") + + subprocess.run(["openocd", "-f", cfg_file]) + +if __name__=="__main__": + main() diff --git a/maxi_dma.py b/maxi_dma.py new file mode 100755 index 0000000..30d55fa --- /dev/null +++ b/maxi_dma.py @@ -0,0 +1,284 @@ +from migen import * +from migen_axi.interconnect import axi +from misoc.interconnect.csr import * +from artiq.gateware import rtio +from operator import attrgetter + + +class MAXI_DMA(Module, AutoCSR): + def __init__(self, bus=None, user=None, trigger_stb=None): + self.bus = bus or axi.Interface(data_width=64) + + self.addr_base = CSRStorage(32) + self.trig_count = CSRStatus(32) + self.write_count = CSRStatus(32) + + # Dout : Data received from CPU, output by DMA module + # Din : Data driven into DMA module, written into CPU + # When stb assert, index shows word being read/written, dout/din holds + # data + # + # Cycle: + # trigger_stb pulsed at start + # Then out_burst_len words are strobed out of dout + # Then, when din_ready is high, in_burst_len words are strobed in to din + self.dout_stb = Signal() + self.din_stb = Signal() + self.dout_index = Signal(max=16) + self.din_index = Signal(max=16) + self.din_ready = Signal() + self.dout = Signal(64) + self.din = Signal(64) + + self.out_burst_len = Signal(max=16) + self.in_burst_len = Signal(max=16) + + ### + self.trigger_stb = trigger_stb + + self.sync += If(trigger_stb, self.trig_count.status.eq(self.trig_count.status+1)) + + if user: + self.comb += user.aruser.eq(0x1f) + self.comb += user.awuser.eq(0x1f) + + ar, aw, w, r, b = attrgetter("ar", "aw", "w", "r", "b")(self.bus) + + ### Read + self.comb += [ + ar.addr.eq(self.addr_base.storage), + self.dout.eq(r.data), + r.ready.eq(1), + ar.burst.eq(axi.Burst.incr.value), + ar.len.eq(self.out_burst_len-1), # Number of transfers in burst (0->1 transfer, 1->2 transfers...) + ar.size.eq(3), # Width of burst: 3 = 8 bytes = 64 bits + ar.cache.eq(0xf), + ] + + # read control + self.submodules.read_fsm = read_fsm = FSM(reset_state="IDLE") + read_fsm.act("IDLE", + If(trigger_stb, + ar.valid.eq(1), + If(ar.ready, + NextState("READ") + ).Else( + NextState("READ_START") + ) + ) + ) + read_fsm.act("READ_START", + ar.valid.eq(1), + If(ar.ready, + NextState("READ"), + ) + ) + read_fsm.act("READ", + ar.valid.eq(0), + If(r.last & r.valid, + NextState("IDLE") + ) + ) + + self.sync += [ + If(read_fsm.ongoing("IDLE"), + self.dout_index.eq(0) + ).Else(If(r.valid & read_fsm.ongoing("READ"), + self.dout_index.eq(self.dout_index+1) + ) + ) + ] + + self.comb += self.dout_stb.eq(r.valid & r.ready) + + ### Write + self.comb += [ + w.data.eq(self.din), + aw.addr.eq(self.addr_base.storage+32), # Write to next cache line + w.strb.eq(0xff), + aw.burst.eq(axi.Burst.incr.value), + aw.len.eq(self.in_burst_len-1), # Number of transfers in burst minus 1 + aw.size.eq(3), # Width of burst: 3 = 8 bytes = 64 bits + aw.cache.eq(0xf), + b.ready.eq(1), + ] + + # write control + self.submodules.write_fsm = write_fsm = FSM(reset_state="IDLE") + write_fsm.act("IDLE", + w.valid.eq(0), + aw.valid.eq(0), + If(trigger_stb, + aw.valid.eq(1), + If(aw.ready, # assumes aw.ready is not randomly deasserted + NextState("DATA_WAIT") + ).Else( + NextState("AW_READY_WAIT") + ) + ) + ) + write_fsm.act("AW_READY_WAIT", + aw.valid.eq(1), + If(aw.ready, + NextState("DATA_WAIT"), + ) + ) + write_fsm.act("DATA_WAIT", + aw.valid.eq(0), + If(self.din_ready, + w.valid.eq(1), + NextState("WRITE") + ) + ) + write_fsm.act("WRITE", + w.valid.eq(1), + If(w.ready & w.last, + NextState("IDLE") + ) + ) + + self.sync += If(w.ready & w.valid, self.write_count.status.eq(self.write_count.status+1)) + + self.sync += [ + If(write_fsm.ongoing("IDLE"), + self.din_index.eq(0) + ), + If(w.ready & w.valid, self.din_index.eq(self.din_index+1)) + ] + + self.comb += [ + w.last.eq(0), + If(self.din_index==aw.len, w.last.eq(1)) + ] + + self.comb += self.din_stb.eq(w.valid & w.ready) + + +class DMA_Test(Module): + def __init__(self, engine=None): + if engine is None: + engine = MAXI_DMA() + + N = 4 + + regs = [Signal(64) for _ in range(N)] + + self.comb += [ + engine.out_burst_len.eq(N), + engine.in_burst_len.eq(N), + ] + + self.sync += [ + If(engine.trigger_stb, engine.din_ready.eq(0)), + If(engine.dout_stb & (engine.dout_index==3), engine.din_ready.eq(1)) + ] + + dout_cases = {} + for i in range(N): + dout_cases[i] = regs[i].eq(engine.dout) + + din_cases = {} + for i in range(N): + din_cases[i] = engine.din.eq(regs[i]) + + self.sync += [ + If(engine.dout_stb, + Case(engine.dout_index, dout_cases) + ), + ] + + self.comb += [ + If(engine.din_stb, + Case(engine.din_index, din_cases) + ) + ] + + +class DMA_KernelInitiator(Module): + def __init__(self, engine=None, cri=None): + self.engine = engine or MAXI_DMA() + self.cri = cri or rtio.cri.Interface() + + ### + cri = self.cri + + self.comb += [ + engine.out_burst_len.eq(4), + engine.in_burst_len.eq(4), + ] + + cmd = Signal(8) + cmd_write = Signal() + cmd_read = Signal() + self.comb += [ + cmd_write.eq(cmd==0), + cmd_read.eq(cmd==1) + ] + + + dout_cases = {} + dout_lw = Signal(32) + dout_hw = Signal(32) + self.comb += [ + dout_lw.eq(engine.dout[:32]), + dout_hw.eq(engine.dout[32:]) + ] + dout_cases[0] = [ + cmd.eq(dout_lw[24:]), + cri.chan_sel.eq(dout_lw[:24]), + cri.o_address.eq(dout_hw[:16]) + ] + dout_cases[1] = [ + cri.timestamp.eq(engine.dout) + ] + dout_cases[2] = [cri.o_data.eq(engine.dout)] # only lowest 64 bits + + self.sync += [ + cri.cmd.eq(rtio.cri.commands["nop"]), + If(engine.dout_stb, + Case(engine.dout_index, dout_cases), + If(engine.dout_index==2, + If(cmd_write, cri.cmd.eq(rtio.cri.commands["write"])), + If(cmd_read, cri.cmd.eq(rtio.cri.commands["read"])) + ) + ) + ] + + # If input event, wait for response before allow input data to be + # sampled + # TODO: If output, wait for wait flag clear + RTIO_I_STATUS_WAIT_STATUS = 4 + RTIO_O_STATUS_WAIT = 1 + + self.submodules.fsm = fsm = FSM(reset_state="IDLE") + + fsm.act("IDLE", + If(engine.trigger_stb, NextState("WAIT_OUT_CYCLE")) + ) + fsm.act("WAIT_OUT_CYCLE", + engine.din_ready.eq(0), + If(engine.dout_stb & (engine.dout_index==3), + NextState("WAIT_READY") + ) + ) + fsm.act("WAIT_READY", + If(cmd_read & (cri.i_status & RTIO_I_STATUS_WAIT_STATUS == 0) \ + | cmd_write & ~(cri.o_status & RTIO_O_STATUS_WAIT), + engine.din_ready.eq(1), + NextState("IDLE") + ) + ) + + din_cases_cmdwrite = { + 0: [engine.din.eq((1<<16) | cri.o_status)], + 1: [engine.din.eq(0)], + } + din_cases_cmdread = { + 0: [engine.din[:32].eq((1<<16) | cri.i_status), engine.din[32:].eq(cri.i_data)], + 1: [engine.din.eq(cri.i_timestamp)] + } + + self.comb += [ + If(cmd_read, Case(engine.din_index, din_cases_cmdread)), + If(cmd_write, Case(engine.din_index, din_cases_cmdwrite)), + ] diff --git a/ps7_init.tcl b/ps7_init.tcl new file mode 100755 index 0000000..1082313 --- /dev/null +++ b/ps7_init.tcl @@ -0,0 +1,771 @@ +proc ps7_pll_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_clock_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000138 0x00000011 0x00000001 + mask_write 0XF8000140 0x03F03F71 0x00100801 + mask_write 0XF800014C 0x00003F31 0x00000501 + mask_write 0XF8000150 0x00003F33 0x00001401 + mask_write 0XF8000154 0x00003F33 0x00001402 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00200500 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01EC044D + mwr -force 0XF8000004 0x0000767B +} +proc ps7_ddr_init_data_3_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000080 + mask_write 0XF8006004 0x0007FFFF 0x00001081 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004159B + mask_write 0XF8006018 0xF7FFFFFF 0x452460D2 + mask_write 0XF800601C 0xFFFFFFFF 0x720238E5 + mask_write 0XF8006020 0x7FDFFFFC 0x270872D0 + mask_write 0XF8006024 0x0FFFFFC3 0x00000000 + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040930 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00000003 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000777 + mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 + mask_write 0XF8006044 0x0FFFFFFF 0x0FF66666 + mask_write 0XF8006048 0x0003F03F 0x0003C008 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x00010000 0x00000000 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF8006078 0x03FFFFFF 0x00466111 + mask_write 0XF800607C 0x000FFFFF 0x00032222 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x00000200 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFCF 0x40000001 + mask_write 0XF800611C 0x7FFFFFCF 0x40000001 + mask_write 0XF8006120 0x7FFFFFCF 0x40000001 + mask_write 0XF8006124 0x7FFFFFCF 0x40000001 + mask_write 0XF800612C 0x000FFFFF 0x00033C03 + mask_write 0XF8006130 0x000FFFFF 0x00034003 + mask_write 0XF8006134 0x000FFFFF 0x0002F400 + mask_write 0XF8006138 0x000FFFFF 0x00030400 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x00000083 + mask_write 0XF8006158 0x000FFFFF 0x00000083 + mask_write 0XF800615C 0x000FFFFF 0x00000080 + mask_write 0XF8006160 0x000FFFFF 0x00000080 + mask_write 0XF8006168 0x001FFFFF 0x00000124 + mask_write 0XF800616C 0x001FFFFF 0x00000125 + mask_write 0XF8006170 0x001FFFFF 0x00000112 + mask_write 0XF8006174 0x001FFFFF 0x00000116 + mask_write 0XF800617C 0x000FFFFF 0x000000C3 + mask_write 0XF8006180 0x000FFFFF 0x000000C3 + mask_write 0XF8006184 0x000FFFFF 0x000000C0 + mask_write 0XF8006188 0x000FFFFF 0x000000C0 + mask_write 0XF8006190 0x6FFFFEFE 0x00040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000703FF 0x000003FF + mask_write 0XF800620C 0x000703FF 0x000003FF + mask_write 0XF8006210 0x000703FF 0x000003FF + mask_write 0XF8006214 0x000703FF 0x000003FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF5 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000081 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000672 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000674 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C + mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B6C 0x00007FFF 0x00000209 + mask_write 0XF8000B70 0x00000001 0x00000001 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FEFFFF 0x00000823 + mask_write 0XF8000700 0x00003FFF 0x00000600 + mask_write 0XF8000704 0x00003FFF 0x00000702 + mask_write 0XF8000708 0x00003FFF 0x00000702 + mask_write 0XF800070C 0x00003FFF 0x00000702 + mask_write 0XF8000710 0x00003FFF 0x00000702 + mask_write 0XF8000714 0x00003FFF 0x00000702 + mask_write 0XF8000718 0x00003FFF 0x00000702 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x00000700 + mask_write 0XF8000724 0x00003FFF 0x00000600 + mask_write 0XF8000728 0x00003FFF 0x00000600 + mask_write 0XF800072C 0x00003FFF 0x00000600 + mask_write 0XF8000730 0x00003FFF 0x00000600 + mask_write 0XF8000734 0x00003FFF 0x00000600 + mask_write 0XF8000738 0x00003FFF 0x00000600 + mask_write 0XF800073C 0x00003FFF 0x00000600 + mask_write 0XF8000740 0x00003FFF 0x00000302 + mask_write 0XF8000744 0x00003FFF 0x00000302 + mask_write 0XF8000748 0x00003FFF 0x00000302 + mask_write 0XF800074C 0x00003FFF 0x00000302 + mask_write 0XF8000750 0x00003FFF 0x00000302 + mask_write 0XF8000754 0x00003FFF 0x00000302 + mask_write 0XF8000758 0x00003FFF 0x00000303 + mask_write 0XF800075C 0x00003FFF 0x00000303 + mask_write 0XF8000760 0x00003FFF 0x00000303 + mask_write 0XF8000764 0x00003FFF 0x00000303 + mask_write 0XF8000768 0x00003FFF 0x00000303 + mask_write 0XF800076C 0x00003FFF 0x00000303 + mask_write 0XF8000770 0x00003FFF 0x00000304 + mask_write 0XF8000774 0x00003FFF 0x00000305 + mask_write 0XF8000778 0x00003FFF 0x00000304 + mask_write 0XF800077C 0x00003FFF 0x00000305 + mask_write 0XF8000780 0x00003FFF 0x00000304 + mask_write 0XF8000784 0x00003FFF 0x00000304 + mask_write 0XF8000788 0x00003FFF 0x00000304 + mask_write 0XF800078C 0x00003FFF 0x00000304 + mask_write 0XF8000790 0x00003FFF 0x00000305 + mask_write 0XF8000794 0x00003FFF 0x00000304 + mask_write 0XF8000798 0x00003FFF 0x00000304 + mask_write 0XF800079C 0x00003FFF 0x00000304 + mask_write 0XF80007A0 0x00003FFF 0x00000380 + mask_write 0XF80007A4 0x00003FFF 0x00000380 + mask_write 0XF80007A8 0x00003FFF 0x00000380 + mask_write 0XF80007AC 0x00003FFF 0x00000380 + mask_write 0XF80007B0 0x00003FFF 0x00000380 + mask_write 0XF80007B4 0x00003FFF 0x00000380 + mask_write 0XF80007B8 0x00003F01 0x00000201 + mask_write 0XF80007BC 0x00003F01 0x00000201 + mask_write 0XF80007C0 0x00003FFF 0x000002E0 + mask_write 0XF80007C4 0x00003FFF 0x000002E1 + mask_write 0XF80007C8 0x00003FFF 0x00000200 + mask_write 0XF80007CC 0x00003FFF 0x00000200 + mask_write 0XF80007D0 0x00003FFF 0x00000280 + mask_write 0XF80007D4 0x00003FFF 0x00000280 + mask_write 0XF8000830 0x003F003F 0x002F002E + mwr -force 0XF8000004 0x0000767B +} +proc ps7_peripherals_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000180 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000180 + mwr -force 0XF8000004 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000003E + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x000003FF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 +} +proc ps7_post_config_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_debug_3_0 {} { + mwr -force 0XF8898FB0 0xC5ACCE55 + mwr -force 0XF8899FB0 0xC5ACCE55 + mwr -force 0XF8809FB0 0xC5ACCE55 +} +proc ps7_pll_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_clock_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000138 0x00000011 0x00000001 + mask_write 0XF8000140 0x03F03F71 0x00100801 + mask_write 0XF800014C 0x00003F31 0x00000501 + mask_write 0XF8000150 0x00003F33 0x00001401 + mask_write 0XF8000154 0x00003F33 0x00001402 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00200500 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01EC044D + mwr -force 0XF8000004 0x0000767B +} +proc ps7_ddr_init_data_2_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000080 + mask_write 0XF8006004 0x1FFFFFFF 0x00081081 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004159B + mask_write 0XF8006018 0xF7FFFFFF 0x452460D2 + mask_write 0XF800601C 0xFFFFFFFF 0x720238E5 + mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 + mask_write 0XF8006024 0x0FFFFFFF 0x0000003C + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040930 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00001FC3 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000777 + mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 + mask_write 0XF8006044 0x0FFFFFFF 0x0FF66666 + mask_write 0XF8006048 0x3FFFFFFF 0x0003C248 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x0001FFFF 0x00000101 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF8006078 0x03FFFFFF 0x00466111 + mask_write 0XF800607C 0x000FFFFF 0x00032222 + mask_write 0XF80060A0 0x00FFFFFF 0x00008000 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x000007FF 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFFF 0x40000001 + mask_write 0XF800611C 0x7FFFFFFF 0x40000001 + mask_write 0XF8006120 0x7FFFFFFF 0x40000001 + mask_write 0XF8006124 0x7FFFFFFF 0x40000001 + mask_write 0XF800612C 0x000FFFFF 0x00033C03 + mask_write 0XF8006130 0x000FFFFF 0x00034003 + mask_write 0XF8006134 0x000FFFFF 0x0002F400 + mask_write 0XF8006138 0x000FFFFF 0x00030400 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x00000083 + mask_write 0XF8006158 0x000FFFFF 0x00000083 + mask_write 0XF800615C 0x000FFFFF 0x00000080 + mask_write 0XF8006160 0x000FFFFF 0x00000080 + mask_write 0XF8006168 0x001FFFFF 0x00000124 + mask_write 0XF800616C 0x001FFFFF 0x00000125 + mask_write 0XF8006170 0x001FFFFF 0x00000112 + mask_write 0XF8006174 0x001FFFFF 0x00000116 + mask_write 0XF800617C 0x000FFFFF 0x000000C3 + mask_write 0XF8006180 0x000FFFFF 0x000000C3 + mask_write 0XF8006184 0x000FFFFF 0x000000C0 + mask_write 0XF8006188 0x000FFFFF 0x000000C0 + mask_write 0XF8006190 0xFFFFFFFF 0x10040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000F03FF 0x000803FF + mask_write 0XF800620C 0x000F03FF 0x000803FF + mask_write 0XF8006210 0x000F03FF 0x000803FF + mask_write 0XF8006214 0x000F03FF 0x000803FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF7 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000081 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000672 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000674 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C + mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B6C 0x00007FFF 0x00000209 + mask_write 0XF8000B70 0x00000021 0x00000021 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FFFFFF 0x00000823 + mask_write 0XF8000700 0x00003FFF 0x00000600 + mask_write 0XF8000704 0x00003FFF 0x00000702 + mask_write 0XF8000708 0x00003FFF 0x00000702 + mask_write 0XF800070C 0x00003FFF 0x00000702 + mask_write 0XF8000710 0x00003FFF 0x00000702 + mask_write 0XF8000714 0x00003FFF 0x00000702 + mask_write 0XF8000718 0x00003FFF 0x00000702 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x00000700 + mask_write 0XF8000724 0x00003FFF 0x00000600 + mask_write 0XF8000728 0x00003FFF 0x00000600 + mask_write 0XF800072C 0x00003FFF 0x00000600 + mask_write 0XF8000730 0x00003FFF 0x00000600 + mask_write 0XF8000734 0x00003FFF 0x00000600 + mask_write 0XF8000738 0x00003FFF 0x00000600 + mask_write 0XF800073C 0x00003FFF 0x00000600 + mask_write 0XF8000740 0x00003FFF 0x00000302 + mask_write 0XF8000744 0x00003FFF 0x00000302 + mask_write 0XF8000748 0x00003FFF 0x00000302 + mask_write 0XF800074C 0x00003FFF 0x00000302 + mask_write 0XF8000750 0x00003FFF 0x00000302 + mask_write 0XF8000754 0x00003FFF 0x00000302 + mask_write 0XF8000758 0x00003FFF 0x00000303 + mask_write 0XF800075C 0x00003FFF 0x00000303 + mask_write 0XF8000760 0x00003FFF 0x00000303 + mask_write 0XF8000764 0x00003FFF 0x00000303 + mask_write 0XF8000768 0x00003FFF 0x00000303 + mask_write 0XF800076C 0x00003FFF 0x00000303 + mask_write 0XF8000770 0x00003FFF 0x00000304 + mask_write 0XF8000774 0x00003FFF 0x00000305 + mask_write 0XF8000778 0x00003FFF 0x00000304 + mask_write 0XF800077C 0x00003FFF 0x00000305 + mask_write 0XF8000780 0x00003FFF 0x00000304 + mask_write 0XF8000784 0x00003FFF 0x00000304 + mask_write 0XF8000788 0x00003FFF 0x00000304 + mask_write 0XF800078C 0x00003FFF 0x00000304 + mask_write 0XF8000790 0x00003FFF 0x00000305 + mask_write 0XF8000794 0x00003FFF 0x00000304 + mask_write 0XF8000798 0x00003FFF 0x00000304 + mask_write 0XF800079C 0x00003FFF 0x00000304 + mask_write 0XF80007A0 0x00003FFF 0x00000380 + mask_write 0XF80007A4 0x00003FFF 0x00000380 + mask_write 0XF80007A8 0x00003FFF 0x00000380 + mask_write 0XF80007AC 0x00003FFF 0x00000380 + mask_write 0XF80007B0 0x00003FFF 0x00000380 + mask_write 0XF80007B4 0x00003FFF 0x00000380 + mask_write 0XF80007B8 0x00003F01 0x00000201 + mask_write 0XF80007BC 0x00003F01 0x00000201 + mask_write 0XF80007C0 0x00003FFF 0x000002E0 + mask_write 0XF80007C4 0x00003FFF 0x000002E1 + mask_write 0XF80007C8 0x00003FFF 0x00000200 + mask_write 0XF80007CC 0x00003FFF 0x00000200 + mask_write 0XF80007D0 0x00003FFF 0x00000280 + mask_write 0XF80007D4 0x00003FFF 0x00000280 + mask_write 0XF8000830 0x003F003F 0x002F002E + mwr -force 0XF8000004 0x0000767B +} +proc ps7_peripherals_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000180 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000180 + mwr -force 0XF8000004 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000003E + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x00000FFF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 +} +proc ps7_post_config_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_debug_2_0 {} { + mwr -force 0XF8898FB0 0xC5ACCE55 + mwr -force 0XF8899FB0 0xC5ACCE55 + mwr -force 0XF8809FB0 0xC5ACCE55 +} +proc ps7_pll_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_clock_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000138 0x00000011 0x00000001 + mask_write 0XF8000140 0x03F03F71 0x00100801 + mask_write 0XF800014C 0x00003F31 0x00000501 + mask_write 0XF8000150 0x00003F33 0x00001401 + mask_write 0XF8000154 0x00003F33 0x00001402 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00200400 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01EC044D + mwr -force 0XF8000004 0x0000767B +} +proc ps7_ddr_init_data_1_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000080 + mask_write 0XF8006004 0x1FFFFFFF 0x00081081 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004159B + mask_write 0XF8006018 0xF7FFFFFF 0x452460D2 + mask_write 0XF800601C 0xFFFFFFFF 0x720238E5 + mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 + mask_write 0XF8006024 0x0FFFFFFF 0x0000003C + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040930 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00001FC3 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000777 + mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 + mask_write 0XF8006044 0x0FFFFFFF 0x0FF66666 + mask_write 0XF8006048 0x3FFFFFFF 0x0003C248 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x0001FFFF 0x00000101 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF80060A0 0x00FFFFFF 0x00008000 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x000007FF 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFFF 0x40000001 + mask_write 0XF800611C 0x7FFFFFFF 0x40000001 + mask_write 0XF8006120 0x7FFFFFFF 0x40000001 + mask_write 0XF8006124 0x7FFFFFFF 0x40000001 + mask_write 0XF800612C 0x000FFFFF 0x00033C03 + mask_write 0XF8006130 0x000FFFFF 0x00034003 + mask_write 0XF8006134 0x000FFFFF 0x0002F400 + mask_write 0XF8006138 0x000FFFFF 0x00030400 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x00000083 + mask_write 0XF8006158 0x000FFFFF 0x00000083 + mask_write 0XF800615C 0x000FFFFF 0x00000080 + mask_write 0XF8006160 0x000FFFFF 0x00000080 + mask_write 0XF8006168 0x001FFFFF 0x00000124 + mask_write 0XF800616C 0x001FFFFF 0x00000125 + mask_write 0XF8006170 0x001FFFFF 0x00000112 + mask_write 0XF8006174 0x001FFFFF 0x00000116 + mask_write 0XF800617C 0x000FFFFF 0x000000C3 + mask_write 0XF8006180 0x000FFFFF 0x000000C3 + mask_write 0XF8006184 0x000FFFFF 0x000000C0 + mask_write 0XF8006188 0x000FFFFF 0x000000C0 + mask_write 0XF8006190 0xFFFFFFFF 0x10040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000F03FF 0x000803FF + mask_write 0XF800620C 0x000F03FF 0x000803FF + mask_write 0XF8006210 0x000F03FF 0x000803FF + mask_write 0XF8006214 0x000F03FF 0x000803FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF7 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000081 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000672 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000674 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C + mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B6C 0x000073FF 0x00000209 + mask_write 0XF8000B70 0x00000021 0x00000021 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FFFFFF 0x00000823 + mask_write 0XF8000700 0x00003FFF 0x00000600 + mask_write 0XF8000704 0x00003FFF 0x00000702 + mask_write 0XF8000708 0x00003FFF 0x00000702 + mask_write 0XF800070C 0x00003FFF 0x00000702 + mask_write 0XF8000710 0x00003FFF 0x00000702 + mask_write 0XF8000714 0x00003FFF 0x00000702 + mask_write 0XF8000718 0x00003FFF 0x00000702 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x00000700 + mask_write 0XF8000724 0x00003FFF 0x00000600 + mask_write 0XF8000728 0x00003FFF 0x00000600 + mask_write 0XF800072C 0x00003FFF 0x00000600 + mask_write 0XF8000730 0x00003FFF 0x00000600 + mask_write 0XF8000734 0x00003FFF 0x00000600 + mask_write 0XF8000738 0x00003FFF 0x00000600 + mask_write 0XF800073C 0x00003FFF 0x00000600 + mask_write 0XF8000740 0x00003FFF 0x00000302 + mask_write 0XF8000744 0x00003FFF 0x00000302 + mask_write 0XF8000748 0x00003FFF 0x00000302 + mask_write 0XF800074C 0x00003FFF 0x00000302 + mask_write 0XF8000750 0x00003FFF 0x00000302 + mask_write 0XF8000754 0x00003FFF 0x00000302 + mask_write 0XF8000758 0x00003FFF 0x00000303 + mask_write 0XF800075C 0x00003FFF 0x00000303 + mask_write 0XF8000760 0x00003FFF 0x00000303 + mask_write 0XF8000764 0x00003FFF 0x00000303 + mask_write 0XF8000768 0x00003FFF 0x00000303 + mask_write 0XF800076C 0x00003FFF 0x00000303 + mask_write 0XF8000770 0x00003FFF 0x00000304 + mask_write 0XF8000774 0x00003FFF 0x00000305 + mask_write 0XF8000778 0x00003FFF 0x00000304 + mask_write 0XF800077C 0x00003FFF 0x00000305 + mask_write 0XF8000780 0x00003FFF 0x00000304 + mask_write 0XF8000784 0x00003FFF 0x00000304 + mask_write 0XF8000788 0x00003FFF 0x00000304 + mask_write 0XF800078C 0x00003FFF 0x00000304 + mask_write 0XF8000790 0x00003FFF 0x00000305 + mask_write 0XF8000794 0x00003FFF 0x00000304 + mask_write 0XF8000798 0x00003FFF 0x00000304 + mask_write 0XF800079C 0x00003FFF 0x00000304 + mask_write 0XF80007A0 0x00003FFF 0x00000380 + mask_write 0XF80007A4 0x00003FFF 0x00000380 + mask_write 0XF80007A8 0x00003FFF 0x00000380 + mask_write 0XF80007AC 0x00003FFF 0x00000380 + mask_write 0XF80007B0 0x00003FFF 0x00000380 + mask_write 0XF80007B4 0x00003FFF 0x00000380 + mask_write 0XF80007B8 0x00003F01 0x00000201 + mask_write 0XF80007BC 0x00003F01 0x00000201 + mask_write 0XF80007C0 0x00003FFF 0x000002E0 + mask_write 0XF80007C4 0x00003FFF 0x000002E1 + mask_write 0XF80007C8 0x00003FFF 0x00000200 + mask_write 0XF80007CC 0x00003FFF 0x00000200 + mask_write 0XF80007D0 0x00003FFF 0x00000280 + mask_write 0XF80007D4 0x00003FFF 0x00000280 + mask_write 0XF8000830 0x003F003F 0x002F002E + mwr -force 0XF8000004 0x0000767B +} +proc ps7_peripherals_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000180 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000180 + mwr -force 0XF8000004 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000003E + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x00000FFF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 +} +proc ps7_post_config_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_debug_1_0 {} { + mwr -force 0XF8898FB0 0xC5ACCE55 + mwr -force 0XF8899FB0 0xC5ACCE55 + mwr -force 0XF8809FB0 0xC5ACCE55 +} +set PCW_SILICON_VER_1_0 "0x0" +set PCW_SILICON_VER_2_0 "0x1" +set PCW_SILICON_VER_3_0 "0x2" +set APU_FREQ 666666667 + + + +proc mask_poll { addr mask } { + set count 1 + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval & $mask}] + while { $maskedval == 0 } { + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval & $mask}] + set count [ expr { $count + 1 } ] + if { $count == 100000000 } { + puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask" + break + } + } +} + + + +proc mask_delay { addr val } { + set delay [ get_number_of_cycles_for_delay $val ] + perf_reset_and_start_timer + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval < $delay}] + while { $maskedval == 1 } { + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval < $delay}] + } + perf_reset_clock +} + +proc ps_version { } { + set si_ver "0x[string range [mrd 0xF8007080] end-8 end]" + set mask_sil_ver "0x[expr {$si_ver >> 28}]" + return $mask_sil_ver; +} + +proc ps7_post_config {} { + + ps7_post_config_1_0 + +} + +proc ps7_debug {} { + ps7_debug_1_0 + +} +proc ps7_init {} { + + ps7_mio_init_data_1_0 + ps7_pll_init_data_1_0 + ps7_clock_init_data_1_0 + ps7_ddr_init_data_1_0 + ps7_peripherals_init_data_1_0 +} + + +# For delay calculation using global timer + +# start timer + proc perf_start_clock { } { + + #writing SCU_GLOBAL_TIMER_CONTROL register + + mask_write 0xF8F00208 0x00000109 0x00000009 +} + +# stop timer and reset timer count regs + proc perf_reset_clock { } { + perf_disable_clock + mask_write 0xF8F00200 0xFFFFFFFF 0x00000000 + mask_write 0xF8F00204 0xFFFFFFFF 0x00000000 +} + +# Compute mask for given delay in miliseconds +proc get_number_of_cycles_for_delay { delay } { + + # GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) + variable APU_FREQ + return [ expr ($delay * $APU_FREQ /(2 * 1000))] +} + + +# stop timer +proc perf_disable_clock {} { + mask_write 0xF8F00208 0xFFFFFFFF 0x00000000 +} + +proc perf_reset_and_start_timer {} { + perf_reset_clock + perf_start_clock +} + + diff --git a/run.py b/run.py new file mode 100755 index 0000000..98400ba --- /dev/null +++ b/run.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python + +import subprocess +import argparse + +def build_experiment(exp, dev_db=None): + output = "firmware/runtime/exp.a" + if not dev_db: + dev_db = "experiments/device_db.py" + subprocess.run(["artiq_compile", "--target", "zynq", "--static", "-o", output, "--device-db", dev_db, exp]) + +def build_firmware(): + subprocess.run(["python", "zedboard.py", "--no-compile-gateware"]) + +def load(): + subprocess.run(["./load.py", "firmware", "run"]) + +parser = argparse.ArgumentParser() +parser.add_argument("path") +args = parser.parse_args() + +build_experiment(args.path) +build_firmware() +load() diff --git a/test_hp_dma.py b/test_hp_dma.py new file mode 100755 index 0000000..664350d --- /dev/null +++ b/test_hp_dma.py @@ -0,0 +1,46 @@ +from migen import * +from hp_dma import * + +def test(dut): + yield from dut.addr_base.write(0x12340) + yield from dut.n_bursts.write(3) + + for _ in range(5): + yield + + yield dut.bus.ar.ready.eq(1) + yield + + yield from dut.trigger.write(1) + + + def deliver_read_word(w, last=False): + yield dut.bus.r.data.eq(w) + yield dut.bus.r.valid.eq(1) + if last: + yield dut.bus.r.last.eq(1) + for _ in range(100): + yield + if (yield dut.bus.r.ready): + yield dut.bus.r.valid.eq(0) + yield dut.bus.r.last.eq(0) + break + + yield + N=(yield dut.bus.ar.len)+1 + + for _ in range( (yield dut.n_bursts.storage)+1 ): + for i in range(N): + yield from deliver_read_word(2*i | (2*i+1)<<32, last=i==N-1) + + for _ in range(5): + yield + + for _ in range(10): + yield + + +if __name__ == "__main__": + dut = HP_DMA_READ() + + run_simulation(dut, test(dut), vcd_name="test.vcd", clocks={"sys": 8}) diff --git a/test_maxi_dma.py b/test_maxi_dma.py new file mode 100755 index 0000000..72cec5e --- /dev/null +++ b/test_maxi_dma.py @@ -0,0 +1,68 @@ +from migen import * +from maxi_dma import * + + + +def test_basic(dut): + yield from dut.engine.addr_base.write(0x12340) + + for _ in range(5): + yield + + yield dut.engine.bus.ar.ready.eq(1) + yield + + yield dut.trigger.eq(1) + + while True: + if (yield dut.engine.bus.ar.valid): + break + yield + yield dut.engine.bus.ar.ready.eq(0) + yield dut.trigger.eq(0) + + def deliver_read_word(w, last=False): + yield dut.engine.bus.r.data.eq(w) + yield dut.engine.bus.r.valid.eq(1) + if last: + yield dut.engine.bus.r.last.eq(1) + for _ in range(100): + yield + if (yield dut.engine.bus.r.ready): + yield dut.engine.bus.r.valid.eq(0) + yield dut.engine.bus.r.last.eq(0) + break + + yield + for i in range(4): + yield from deliver_read_word(2*i | (2*i+1)<<32, last=i==3) + + for _ in range(5): + yield + + while True: + if (yield dut.engine.bus.aw.valid): + break + yield + yield dut.engine.bus.aw.ready.eq(1) + yield + yield dut.engine.bus.aw.ready.eq(0) + + yield dut.engine.bus.w.ready.eq(1) + + for _ in range(10): + yield + + +class Wrapper(Module): + def __init__(self): + self.trigger = Signal() + + self.submodules.engine = MAXI_DMA(trigger_stb=self.trigger) + self.submodules.dma_test = DMA_Test(self.engine) + + +if __name__ == "__main__": + dut = Wrapper() + + run_simulation(dut, test_basic(dut), vcd_name="test.vcd", clocks={"sys": 8}) diff --git a/test_rtio_dma.py b/test_rtio_dma.py new file mode 100755 index 0000000..b2ca64d --- /dev/null +++ b/test_rtio_dma.py @@ -0,0 +1,79 @@ +from migen import * +from maxi_dma import * + + + + +def test(dut): + def delay_cycles(N): + for _ in range(N): + yield + + yield from delay_cycles(4) + + yield dut.trigger_stb.eq(1) + yield + yield dut.trigger_stb.eq(0) + + yield from delay_cycles(2) + + assert (yield dut.din_ready)==0 + + douts = [ + (0x2<<32) | (1<< 24) | 1, # address, cmd, channel + 0x55, # timestamp + 0x111111, # Data + 0x0 + ] + + yield dut.dout_stb.eq(1) + for i in range( (yield dut.out_burst_len) ): + yield dut.dout_index.eq(i) + yield dut.dout.eq(douts[i]) + yield + yield dut.dout_stb.eq(0) + + # yield dut.h.cri.o_status.eq(0x3) + yield from delay_cycles(10) + yield dut.h.cri.i_data.eq(1) + yield dut.h.cri.i_timestamp.eq(2) + yield dut.h.cri.i_status.eq(4) + + while True: + if (yield dut.din_ready): + break + yield + + yield dut.din_stb.eq(1) + print("Got: ") + dins = [] + for i in range( (yield dut.in_burst_len) ): + yield dut.din_index.eq(i) + yield + dins.append( (yield dut.din) ) + yield dut.din_stb.eq(0) + print(dins) + + + +class Wrapper(Module): + def __init__(self): + self.dout_stb = Signal() + self.din_stb = Signal() + self.dout_index = Signal(max=16) + self.din_index = Signal(max=16) + self.din_ready = Signal() + self.dout = Signal(64) + self.din = Signal(64) + + self.out_burst_len = Signal(max=16) + self.in_burst_len = Signal(max=16) + + self.trigger_stb = Signal() + + self.submodules.h = DMA_KernelInitiator(self) + + +if __name__ == "__main__": + dut = Wrapper() + run_simulation(dut, test(dut), vcd_name="test_rtio_dma.vcd", clocks={"sys": 8}) diff --git a/xilinx-tcl.cfg b/xilinx-tcl.cfg new file mode 100755 index 0000000..e326d99 --- /dev/null +++ b/xilinx-tcl.cfg @@ -0,0 +1,61 @@ +# +# TCL to allow the Xilinx PS7 Init TCL code to run in OpenOCD. +# + +proc mrd { args } { + if {[llength $args] == 0} { + echo "mrd address \[count \[w|h|b\]\]" + echo " Read memory locations starting at
. Defaults to one word." + return + } + set addr [lindex $args 0] + set count 1 + set bits 32 + if {[llength $args] > 1} { + set count [lindex $args 1] + if {[llength $args] > 2} { + switch [lindex $args 2] { + w { set bits 32 } + h { set bits 16 } + b { set bits 8 } + default { set bits 32 } + } + } + } + mem2array x $bits $addr $count + set nibbles [expr {$bits / 4}] + set bytes [expr {$bits / 8}] + set result {} + foreach {idx elmt} $x { + append result [format "%08x: %0*x\n" [expr {$addr + $idx * $bytes}] $nibbles $elmt] + } + return $result +} + +proc mwr { args } { + set addr [lindex $args 1] + set data [lindex $args 2] + mww $addr $data +} + +proc mask_write { addr mask value } { + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval & ~$mask}] + #echo "curval = [format 0x%08x $curval] maskedval = [format 0x%08x $maskedval]" + set writeval(0) [expr {$maskedval | $value}] + #echo " $addr <= [format 0x%08x $writeval(0)] ([format 0x%08x $curval]: [format 0x%08x $mask]/[format 0x%08x $value])" + array2mem writeval 32 $addr 1 +} + +proc xilinx_ps7_init { } { + poll off + reset init + reset halt + targets zynq.cpu.0 + sleep 100 + halt + ps7_debug + ps7_init + ps7_post_config + poll on +} \ No newline at end of file diff --git a/zedboard.py b/zedboard.py new file mode 100755 index 0000000..cc0b819 --- /dev/null +++ b/zedboard.py @@ -0,0 +1,180 @@ +from migen_axi.integration.soc_core import SoCCore +from migen_axi.platforms import zedboard +from migen import * +from misoc.interconnect.csr import * +from migen.genlib.resetsync import AsyncResetSynchronizer +from migen.genlib.cdc import MultiReg + +from misoc.integration.builder import * + +from artiq.gateware import rtio +from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, spi2 +from artiq.gateware import eem + +from artiq.gateware.rtio.phy import ttl_serdes_7series, ttl_simple +from artiq.gateware import fmcdio_vhdci_eem + +from maxi_dma import MAXI_DMA, DMA_KernelInitiator, DMA_Test +from hp_dma import HP_DMA_READ +from operator import attrgetter + +import argparse +import os + + +class _RTIOCRG(Module, AutoCSR): + def __init__(self): + self._pll_reset = CSRStorage(reset=1) + self._pll_locked = CSRStatus() + self.clock_domains.cd_sys = ClockDomain() + self.clock_domains.cd_rtio = ClockDomain() + # self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True) + + pll_locked = Signal() + rtio_clk = Signal() + rtiox4_clk = Signal() + self.specials += [ + Instance("PLLE2_ADV", + p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked, + + p_REF_JITTER1=0.24, + p_CLKIN1_PERIOD=8.0, p_CLKIN2_PERIOD=8.0, + i_CLKIN2=self.cd_sys.clk, + # Warning: CLKINSEL=0 means CLKIN2 is selected + i_CLKINSEL=0, + + # VCO @ 1GHz when using 125MHz input + p_CLKFBOUT_MULT=8, p_DIVCLK_DIVIDE=1, + i_CLKFBIN=self.cd_rtio.clk, + i_RST=self._pll_reset.storage, + + o_CLKFBOUT=rtio_clk, + + # p_CLKOUT0_DIVIDE=2, p_CLKOUT0_PHASE=0.0, + # o_CLKOUT0=rtiox4_clk + ), + Instance("BUFG", i_I=rtio_clk, o_O=self.cd_rtio.clk), + # Instance("BUFG", i_I=rtiox4_clk, o_O=self.cd_rtiox4.clk), + + AsyncResetSynchronizer(self.cd_rtio, ~pll_locked), + MultiReg(pll_locked, self._pll_locked.status) + ] + + +def fix_serdes_timing_path(platform): + # ignore timing of path from OSERDESE2 through the pad to ISERDESE2 + platform.add_platform_command( + "set_false_path -quiet " + "-through [get_pins -filter {{REF_PIN_NAME == OQ || REF_PIN_NAME == TQ}} " + "-of [get_cells -filter {{REF_NAME == OSERDESE2}}]] " + "-to [get_pins -filter {{REF_PIN_NAME == D}} " + "-of [get_cells -filter {{REF_NAME == ISERDESE2}}]]" + ) + + + +class Zedboard(SoCCore): + def __init__(self): + plat = zedboard.Platform() + super().__init__(platform=plat) + + fclk0 = self.ps7.fclk.clk[0] + self.clock_domains.cd_sys = ClockDomain() + self.specials += Instance("BUFG", i_I=fclk0, o_O=self.cd_sys.clk), + plat.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]") + plat.add_platform_command("set_input_jitter clk_fpga_0 0.24") + + self.evento_stb = Signal() + evento_latched = Signal() + evento_latched_d = Signal() + self.sync += evento_latched.eq(self.ps7.event.o) + self.sync += evento_latched_d.eq(evento_latched) + self.comb += self.evento_stb.eq(evento_latched != evento_latched_d) + + self.submodules.hp_dma = HP_DMA_READ(bus=self.ps7.s_axi_hp0) + self.csr_devices.append("hp_dma") + + # Debug ports + # pads_b = plat.request("pmod",1) + # ar, aw, w, r, b = attrgetter("ar", "aw", "w", "r", "b")(self.dma.bus) + # self.comb += pads_b[0].eq(self.dma.trigger_stb) + + plat.add_extension(fmcdio_vhdci_eem.io) + plat.add_connectors(fmcdio_vhdci_eem.connectors) + + self.rtio_channels = [] + + for i in range(4): + pad = plat.request("user_led", i) + phy = ttl_simple.InOut(pad) + self.submodules += phy + self.rtio_channels.append(rtio.Channel.from_phy(phy)) + + for i in range(4): + led = plat.request("user_led", i+4) + s = Signal() + btn = plat.request("user_btn", i) + self.comb += led.eq(s | btn) + self.comb += s.eq(self.ps7.gpio.o[i]) + + pads = plat.request("pmod",0) + for i in range(8): + phy = ttl_simple.InOut(pads[i]) + self.submodules += phy + self.rtio_channels.append(rtio.Channel.from_phy(phy)) + + ttl_phy = ttl_simple.Output + eem.Urukul.add_std(self, 0, 1, ttl_phy, iostandard="LVDS_25") + eem.Urukul.add_std(self, 2, 3, ttl_phy, iostandard="LVDS_25") + + self.add_rtio(self.rtio_channels) + + + def add_rtio(self, rtio_channels): + self.submodules.rtio_crg = _RTIOCRG() + self.csr_devices.append("rtio_crg") + + self.submodules.rtio_core = rtio.Core(rtio_channels) + self.csr_devices.append("rtio_core") + self.submodules.rtio = rtio.KernelInitiator() + self.csr_devices.append("rtio") + + self.submodules.dma = MAXI_DMA(bus=self.ps7.s_axi_acp, + user=self.ps7.s_axi_acp_user, + trigger_stb=self.evento_stb) + self.csr_devices.append("dma") + self.submodules.rtio_dma = DMA_KernelInitiator(engine=self.dma) + + self.submodules.cri_con = rtio.CRIInterconnectShared( + [self.rtio.cri, self.rtio_dma.cri], + [self.rtio_core.cri]) + self.csr_devices.append("cri_con") + + self.platform.add_false_path_constraints( + self.rtio_crg.cd_rtio.clk) + + self.comb += self.rtio_crg.cd_sys.clk.eq(self.cd_sys.clk) + + + + +def main(): + parser = argparse.ArgumentParser() + builder_args(parser) + args = parser.parse_args() + + soc = Zedboard() + + builder = Builder(soc, **builder_argdict(args)) + builder.software_packages = [] + root_path = os.path.dirname(os.path.abspath(__file__)) + builder.add_software_package("libm") + builder.add_software_package("libprintf") + builder.add_software_package("libunwind") + builder.add_software_package("libbase") + builder.add_software_package("runtime", os.path.join(root_path, "firmware/runtime")) + builder.build() + + +if __name__ == "__main__": + main() diff --git a/zynq-7000.cfg b/zynq-7000.cfg new file mode 100644 index 0000000..9227c0a --- /dev/null +++ b/zynq-7000.cfg @@ -0,0 +1,211 @@ +# +# Xilinx Zynq 7000 SoC +# +# Chris Johns +# +# Setup +# ----- +# +# Create a user configuration following the "Configuration Basics" in the user +# documentation. In the file have: +# +# source [find interface/ftdi/flyswatter2.cfg] +# source [find board/zynq-zc706-eval.cfg] +# adapter_khz 2000 +# init +# + +if { [info exists CHIPNAME] } { + global _CHIPNAME + set _CHIPNAME $CHIPNAME +} else { + global _CHIPNAME + set _CHIPNAME zynq +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + # this defaults to a bigendian + set _ENDIAN little +} + +if { [info exists SMP] } { + global _SMP + set _SMP 1 +} else { + global _SMP + set _SMP 0 +} + +# +# PL Tap. +# +# See ug585 ZYNQ-7000 TRM PSS_IDCODE for how this number is constructed. +# 0x03731093 - ZC706 Eval board 1.1 +# 0x23731093 - ?? +# 0x23727093 - Zedboard Rev. C and D +# +# Set in your configuration file or board specific file. +# +if { [info exists PL_TAPID] } { + set _PL_TAPID $PL_TAPID +} else { + set _PL_TAPID 0x03731093 +} + +jtag newtap $_CHIPNAME tap -irlen 6 -ircapture 0x001 -irmask 0x003 \ + -expected-id $_PL_TAPID + +# +# CoreSight Debug Access Port +# +if { [info exists DAP_TAPID] } { + set _DAP_TAPID $DAP_TAPID +} else { + set _DAP_TAPID 0x4ba00477 +} + +jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x01 -irmask 0x03 \ + -expected-id $_DAP_TAPID + +# +# GDB target: Cortex-A9, using DAP, configuring only one core +# Base addresses of cores: +# core 0 - 0xF8890000 +# core 1 - 0xF8892000 +# +# Read from the ROM table with the patch to read the nested table. +# + +set _TARGETNAME_0 $_CHIPNAME.cpu.0 +set _TARGETNAME_1 $_CHIPNAME.cpu.1 + +target create $_TARGETNAME_0 cortex_a -coreid 0 \ + -endian $_ENDIAN \ + -chain-position $_CHIPNAME.dap \ + -dbgbase 0x80090000 +if { $_SMP } { + echo "Zynq CPU1." + target create $_TARGETNAME_1 cortex_a -coreid 1 \ + -endian $_ENDIAN \ + -chain-position $_CHIPNAME.dap \ + -dbgbase 0x80092000 + target smp $_TARGETNAME_0 $_TARGETNAME_1 +} + +# +# Hack to get the registers into a stable state when first booting a zynq in +# JTAG mode. If r11 is pointing to an invalid address and you use gdb to set a +# register the write will fail because gdb attempts to scan or unwind the +# current frame and the bad address seems to lock the bus up. This code puts +# the registers into the OCM and hopefull safe. +# +proc zynq_clear_registers { target } { + echo "Zynq-7000 Series setup: $target" + set _OCM_END 0x0003FFF0 + mww phys 0xF8007000 0x4E00E07F + reg r0 0 + reg r1 0 + reg r2 0 + reg r3 0 + reg r4 0 + reg r5 0 + reg r6 0 + reg r7 0 + reg r8 0 + reg r9 0 + reg r10 0 + reg r11 $_OCM_END + reg sp_svc $_OCM_END + reg lr_svc $_OCM_END + reg sp_abt $_OCM_END + reg lr_abt $_OCM_END + reg sp_und $_OCM_END + reg lr_und $_OCM_END +} + +proc zynq_disable_mmu_and_caches { target } { + # arm mcr pX op1 CRn CRm op2 value + echo "Disable MMU and caches" + # Invalidate caches + catch { + $target arm mcr 15 0 7 5 0 0 + $target arm mcr 15 0 7 7 0 0 + # Invalidate all TLBs + $target arm mcr 15 0 8 5 0 0 + $target arm mcr 15 0 8 6 0 0 + $target arm mcr 15 0 8 7 0 0 + $target arm mcr 15 4 8 3 0 0 + $target arm mcr 15 4 8 7 0 0 + set cp [$target arm mrc 15 0 1 0 0] + echo "SCTRL => [format 0x%x $cp]" + set mask [expr 1 << 29 | 1 << 12 | 1 << 11 | 1 << 2 | 1 << 1 | 1 << 0] + set cp [expr ($cp & ~$mask)] + $target arm mcr 15 0 1 0 0 $cp + echo "SCTRL <= [format 0x%x $cp]" + } +} + +proc zynq_boot_ocm_setup { } { + # + # Enable the OCM + # + echo "Zynq Boot OCM setup" + catch { + mww phys 0xF8000008 0xDF0D + mww phys 0xF8000238 0 + mww phys 0xF8000910 0xC + } +} + +proc zynq_rtems_setup { } { + cache_config l2x 0xF8F02000 8 + cortex_a maskisr on +} + +proc zynq_restart { wait } { + global _SMP + global _TARGETNAME_0 + global _TARGETNAME_1 + set target0 $_TARGETNAME_0 + set target1 $_TARGETNAME_1 + echo "Zynq reset, resetting the board ... " + poll off + # + # Issue the reset via the SLCR + # + catch { + mww phys 0xF8000008 0xDF0D + mww phys 0xF8000200 1 + } + echo "Zynq reset waiting for $wait msecs ... " + sleep $wait + # + # Reconnect the DAP etc due to the reset. + # + $target0 cortex_a dbginit + $target0 arm core_state arm + if { $_SMP } { + $target1 arm core_state arm + $target1 cortex_a dbginit + cortex_a smp_off + } + poll on + # + # We can now halt the core. + # + if { $_SMP } { + targets $target1 + halt + } + targets $target0 + halt + zynq_rtems_setup +} + +proc zynq_gdb_attach { target } { + catch { + halt + } +} \ No newline at end of file