69 lines
1.5 KiB
Python
69 lines
1.5 KiB
Python
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from migen import *
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from maxi_dma import *
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def test_basic(dut):
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yield from dut.engine.addr_base.write(0x12340)
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for _ in range(5):
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yield
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yield dut.engine.bus.ar.ready.eq(1)
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yield
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yield dut.trigger.eq(1)
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while True:
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if (yield dut.engine.bus.ar.valid):
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break
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yield
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yield dut.engine.bus.ar.ready.eq(0)
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yield dut.trigger.eq(0)
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def deliver_read_word(w, last=False):
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yield dut.engine.bus.r.data.eq(w)
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yield dut.engine.bus.r.valid.eq(1)
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if last:
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yield dut.engine.bus.r.last.eq(1)
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for _ in range(100):
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yield
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if (yield dut.engine.bus.r.ready):
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yield dut.engine.bus.r.valid.eq(0)
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yield dut.engine.bus.r.last.eq(0)
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break
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yield
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for i in range(4):
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yield from deliver_read_word(2*i | (2*i+1)<<32, last=i==3)
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for _ in range(5):
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yield
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while True:
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if (yield dut.engine.bus.aw.valid):
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break
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yield
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yield dut.engine.bus.aw.ready.eq(1)
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yield
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yield dut.engine.bus.aw.ready.eq(0)
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yield dut.engine.bus.w.ready.eq(1)
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for _ in range(10):
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yield
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class Wrapper(Module):
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def __init__(self):
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self.trigger = Signal()
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self.submodules.engine = MAXI_DMA(trigger_stb=self.trigger)
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self.submodules.dma_test = DMA_Test(self.engine)
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if __name__ == "__main__":
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dut = Wrapper()
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run_simulation(dut, test_basic(dut), vcd_name="test.vcd", clocks={"sys": 8})
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