2019-08-23 18:47:46 +08:00
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#!/usr/bin/env python
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2018-10-05 05:19:23 +08:00
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from migen import *
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from maxi_dma import *
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def test(dut):
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def delay_cycles(N):
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for _ in range(N):
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yield
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yield from delay_cycles(4)
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yield dut.trigger_stb.eq(1)
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yield
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yield dut.trigger_stb.eq(0)
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yield from delay_cycles(2)
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assert (yield dut.din_ready)==0
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douts = [
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(0x2<<32) | (1<< 24) | 1, # address, cmd, channel
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0x55, # timestamp
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0x111111, # Data
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0x0
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]
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yield dut.dout_stb.eq(1)
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for i in range( (yield dut.out_burst_len) ):
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yield dut.dout_index.eq(i)
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yield dut.dout.eq(douts[i])
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yield
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yield dut.dout_stb.eq(0)
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# yield dut.h.cri.o_status.eq(0x3)
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yield from delay_cycles(10)
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yield dut.h.cri.i_data.eq(1)
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yield dut.h.cri.i_timestamp.eq(2)
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yield dut.h.cri.i_status.eq(4)
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while True:
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if (yield dut.din_ready):
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break
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yield
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yield dut.din_stb.eq(1)
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print("Got: ")
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dins = []
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for i in range( (yield dut.in_burst_len) ):
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yield dut.din_index.eq(i)
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yield
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dins.append( (yield dut.din) )
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yield dut.din_stb.eq(0)
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print(dins)
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class Wrapper(Module):
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def __init__(self):
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self.dout_stb = Signal()
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self.din_stb = Signal()
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self.dout_index = Signal(max=16)
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self.din_index = Signal(max=16)
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self.din_ready = Signal()
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self.dout = Signal(64)
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self.din = Signal(64)
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self.out_burst_len = Signal(max=16)
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self.in_burst_len = Signal(max=16)
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self.trigger_stb = Signal()
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self.submodules.h = DMA_KernelInitiator(self)
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if __name__ == "__main__":
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dut = Wrapper()
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run_simulation(dut, test(dut), vcd_name="test_rtio_dma.vcd", clocks={"sys": 8})
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