107 lines
3.4 KiB
Python
107 lines
3.4 KiB
Python
from nmigen import *
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__all__ = ["EthRGMIICoreCfg", "SPIFlashCoreCfg"]
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class EthRGMIICoreCfg(Elaboratable):
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def __init__(self, core, eth_pins, *, rx, tx, tx_clk=None):
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self.core = core
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self.eth_pins = eth_pins
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if not isinstance(rx, bool):
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raise TypeError("Must include either rx=True or False "
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"to indicate whether RX is used or not, not rx={}"
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.format(repr(rx)))
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self.rx = rx
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if not isinstance(tx, bool):
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raise TypeError("Must include either tx=True or False "
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"to indicate whether TX is used or not, not tx={}"
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.format(repr(tx)))
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self.tx = tx
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if tx:
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if tx_clk is None:
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raise TypeError("Signal as TX clock must not be None")
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self.tx_clk = tx_clk
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def elaborate(self, platform):
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m = Module()
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if self.rx:
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rx = self.core.rx_io
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# DDRInput on rx_ctl
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m.submodules += [
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Instance("IDDRX1F",
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i_D=self.eth_pins.rx_ctl,
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i_SCLK=rx.rx_ctl_iddr.i_clk,
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o_Q0=rx.rx_ctl_iddr.i0,
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o_Q1=rx.rx_ctl_iddr.i1,
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)
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]
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# DDRInput on rx_data
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for i in range(4):
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m.submodules += [
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Instance("IDDRX1F",
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i_D=self.eth_pins.rx_data[i],
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i_SCLK=rx.rx_data_iddr.i_clk,
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o_Q0=rx.rx_data_iddr.i0[i],
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o_Q1=rx.rx_data_iddr.i1[i],
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)
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]
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# RX Clock
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cd_eth_rx = ClockDomain("eth_rx")
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m.domains += cd_eth_rx
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m.d.comb += cd_eth_rx.clk.eq(self.eth_pins.rx_clk)
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if self.tx:
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tx = self.core.tx_io
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# DDROutput on tx_clk
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m.submodules += [
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Instance("ODDRX1F",
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i_D0=tx.tx_clk_oddr.o0,
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i_D1=tx.tx_clk_oddr.o1,
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i_SCLK=tx.tx_clk_oddr.o_clk,
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o_Q=self.eth_pins.tx_clk
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)
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]
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# DDROutput on tx_ctl
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m.submodules += [
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Instance("ODDRX1F",
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i_D0=tx.tx_ctl_oddr.o0,
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i_D1=tx.tx_ctl_oddr.o1,
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i_SCLK=tx.tx_ctl_oddr.o_clk,
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o_Q=self.eth_pins.tx_ctl
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)
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]
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# DDROutput on tx_data
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for i in range(4):
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m.submodules += [
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Instance("ODDRX1F",
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i_D0=tx.tx_data_oddr.o0[i],
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i_D1=tx.tx_data_oddr.o1[i],
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i_SCLK=tx.tx_data_oddr.o_clk,
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o_Q=self.eth_pins.tx_data[i]
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)
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]
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# TX Clock
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cd_eth_tx = ClockDomain("eth_tx")
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m.domains += cd_eth_tx
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m.d.comb += cd_eth_tx.clk.eq(self.tx_clk)
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return m
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class SPIFlashCoreCfg(Elaboratable):
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def __init__(self, core):
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self.core = core
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def elaborate(self, platform):
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m = Module()
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spi = self.core.spi_io
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m.submodules += Instance("USRMCLK",
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i_USRMCLKI=spi.clk,
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i_USRMCLKTS=0)
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return m
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