52 lines
1.4 KiB
Python
52 lines
1.4 KiB
Python
from nmigen import *
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from nmigen.back import verilog
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from heavycomps import uart
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class Top(Elaboratable):
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def __init__(self, baudrate=115200):
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self.baudrate = baudrate
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self.clk156_p = Signal()
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self.clk156_n = Signal()
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self.serial_tx = Signal()
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def elaborate(self, platform):
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m = Module()
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cd_sync = ClockDomain(reset_less=True)
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m.domains += cd_sync
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m.submodules.clock = Instance("IBUFGDS",
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i_I=self.clk156_p, i_IB=self.clk156_n, o_O=cd_sync.clk)
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string = "Hello World!\r\n"
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mem = Memory(width=8, depth=len(string),
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init=[ord(c) for c in string])
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m.submodules.rdport = rdport = mem.read_port(synchronous=False)
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tx = uart.RS232TX(round(2**32*self.baudrate/156e6))
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m.submodules.tx = tx
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m.d.comb += [
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tx.stb.eq(1),
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tx.data.eq(rdport.data),
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self.serial_tx.eq(tx.tx)
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]
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with m.If(tx.ack):
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with m.If(rdport.addr == len(string) - 1):
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m.d.sync += rdport.addr.eq(0)
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with m.Else():
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m.d.sync += rdport.addr.eq(rdport.addr + 1)
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return m
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def main():
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top = Top()
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output = verilog.convert(Fragment.get(top, None),
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ports=(top.clk156_p, top.clk156_n, top.serial_tx))
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print(output)
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if __name__ == "__main__":
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main()
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