49 lines
1.4 KiB
Nix
49 lines
1.4 KiB
Nix
{ pkgs ? import <nixpkgs> {}
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, hx ? import ../default.nix { inherit pkgs; }}:
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let
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vivadoInput = pkgs.runCommand "helloworld-vivado-input" {
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buildInputs = [ (pkgs.python3.withPackages(ps: [hx.nmigen hx.heavycomps])) hx.yosys ];
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}
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''
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mkdir $out
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python ${./helloworld_kintex7.py} > $out/top.v
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cat > $out/top.xdc << EOF
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set_property LOC K24 [get_ports serial_tx]
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set_property IOSTANDARD LVCMOS25 [get_ports serial_tx]
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set_property LOC K28 [get_ports clk156_p]
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set_property IOSTANDARD LVDS_25 [get_ports clk156_p]
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set_property DIFF_TERM TRUE [get_ports clk156_p]
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set_property LOC K29 [get_ports clk156_n]
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set_property IOSTANDARD LVDS_25 [get_ports clk156_n]
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set_property DIFF_TERM TRUE [get_ports clk156_n]
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create_clock -name clk156 -period 6.4 [get_nets clk156_p]
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EOF
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cat > $out/top.tcl << EOF
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create_project -force -name top -part xc7k325t-ffg900-2
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set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project]
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add_files {top.v}
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set_property library work [get_files {top.v}]
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read_xdc top.xdc
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synth_design -top top -part xc7k325t-ffg900-2
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opt_design
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place_design
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route_design
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set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
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set_property BITSTREAM.GENERAL.COMPRESS True [current_design]
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write_bitstream -force top.bit
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quit
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EOF
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'';
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in
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hx.vivado.buildBitstream {
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name = "helloworld-bitstream";
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src = vivadoInput;
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}
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