59 lines
1.5 KiB
Python
59 lines
1.5 KiB
Python
import argparse
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from nmigen import *
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from nmigen_boards.versa_ecp5 import VersaECP5Platform
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from heavycomps import uart
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class Top(Elaboratable):
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def __init__(self, baudrate=115200):
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self.baudrate = baudrate
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def elaborate(self, platform):
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m = Module()
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cd_sync = ClockDomain(reset_less=True)
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m.domains += cd_sync
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m.d.comb += cd_sync.clk.eq(platform.request("clk100").i)
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string = "Hello World!\r\n"
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mem = Memory(width=8, depth=len(string),
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init=[ord(c) for c in string])
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m.submodules.rdport = rdport = mem.read_port(domain="comb")
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wait = Signal()
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tx = uart.RS232TX(round(2**32*self.baudrate/100e6))
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m.submodules.tx = tx
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m.d.comb += [
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tx.stb.eq(~wait),
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tx.data.eq(rdport.data),
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platform.request("uart").tx.o.eq(tx.tx)
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]
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release = Signal()
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counter = Signal(25)
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m.d.sync += Cat(counter, release).eq(counter + 1)
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with m.If(release):
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m.d.sync += wait.eq(0)
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with m.If(~wait & tx.ack):
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with m.If(rdport.addr == len(string) - 1):
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m.d.sync += rdport.addr.eq(0)
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m.d.sync += wait.eq(1)
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with m.Else():
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m.d.sync += rdport.addr.eq(rdport.addr + 1)
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return m
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def main():
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parser = argparse.ArgumentParser()
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parser.add_argument("build_dir")
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args = parser.parse_args()
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VersaECP5Platform().build(Top(), build_dir=args.build_dir)
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if __name__ == "__main__":
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main()
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