75 lines
2.1 KiB
Python
75 lines
2.1 KiB
Python
from nmigen import *
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from nmigen.back import rtlil
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from heavycomps import uart, wishbone
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from minerva.core import Minerva
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class SimpleWishboneSerial(Elaboratable):
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def __init__(self, tx, sys_clk_freq, baudrate=115200):
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self.tx = tx
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self.bus = wishbone.Interface()
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self.ftw = round(2**32*baudrate/sys_clk_freq)
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def elaborate(self, platform):
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m = Module()
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m.submodules.tx = tx = uart.RS232TX(self.ftw)
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m.d.comb += [
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tx.stb.eq(self.bus.cyc & self.bus.stb & self.bus.we),
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tx.data.eq(self.bus.dat_w),
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self.bus.ack.eq(tx.ack),
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self.tx.eq(tx.tx)
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]
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return m
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class Top(Elaboratable):
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def __init__(self):
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self.clk100 = Signal()
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self.serial_tx = Signal()
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def elaborate(self, platform):
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m = Module()
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cd_sync = ClockDomain(reset_less=True)
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m.domains += cd_sync
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m.d.comb += cd_sync.clk.eq(self.clk100)
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m.submodules.cpu = cpu = Minerva(with_icache=False, with_dcache=False)
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m.submodules.ram = ram = wishbone.SRAM(Memory(32, 1024))
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m.submodules.uart = uart = SimpleWishboneSerial(self.serial_tx, 100e6)
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m.submodules.con = con = wishbone.InterconnectShared(
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[cpu.ibus, cpu.dbus],
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[
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(lambda a: ~a[20], ram.bus),
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(lambda a: a[20], uart.bus)
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], register=True)
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# work around https://github.com/m-labs/nmigen/issues/30
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m.d.comb += [
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cpu.external_interrupt.eq(0),
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cpu.timer_interrupt.eq(0),
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cpu.fetch.ibus.dat_w.eq(0),
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cpu.fetch.ibus.sel.eq(0b1111),
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cpu.fetch.ibus.we.eq(0),
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cpu.fetch.ibus.cti.eq(0),
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cpu.fetch.ibus.bte.eq(0),
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cpu.loadstore.dbus.cti.eq(0),
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cpu.loadstore.dbus.bte.eq(0),
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ram.bus.err.eq(0),
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uart.bus.err.eq(0),
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uart.bus.dat_r.eq(0)
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]
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return m
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def main():
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top = Top()
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output = rtlil.convert(Fragment.get(top, None),
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ports=(top.clk100, top.serial_tx))
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print(output)
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if __name__ == "__main__":
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main()
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