69 lines
2.4 KiB
Python
69 lines
2.4 KiB
Python
from nmigen import *
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from nmigen_soc import csr
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from nmigen.utils import *
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__all__ = ["TimerCore"]
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class TimerCore(Elaboratable):
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def __init__(self, *, width, bus_data_width,
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clk_domain="sync", bus_granularity=None):
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self.width = width
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bus_dw = bus_data_width
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if bus_granularity is None:
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bus_granularity = bus_data_width
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bus_gr = bus_granularity
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with csr.Bank(name="timer",
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addr_width=log2_int(-(-(bus_dw+3*max(width, bus_dw))//bus_gr), need_pow2=False),
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data_width=bus_gr) as self.csr:
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self.csr.r += [
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csr.Register(
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"control", "rw", width=bus_dw,
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fields=[csr.Field("enable", startbit=0),
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csr.Field("update_enable", startbit=4)]
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),
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csr.Register(
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"load", "rw", width=max(width, bus_dw),
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fields=[csr.Field("value", width=self.width)]
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),
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csr.Register(
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"reload", "rw", width=max(width, bus_dw),
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fields=[csr.Field("value", width=self.width)]
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),
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csr.Register(
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"current", "r", width=max(width, bus_dw),
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fields=[csr.Field("value", width=self.width)]
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)
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]
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self.wb2csr = csr.WishboneCSRBridge(self.csr.dec.bus, data_width=bus_data_width)
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self.csr_bus = self.wb2csr.wb_bus
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def elaborate(self, platform):
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m = Module()
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m.submodules += self.csr, self.wb2csr
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# Value right now
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value = Signal(self.width)
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# When Timer is enabled, start counting
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with m.If(self.csr.r.control.f.enable.s):
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with m.If(value == 0):
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m.d.sync += value.eq(self.csr.r.reload.s)
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with m.Else():
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m.d.sync += value.eq(value - 1)
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# Otherwise, load Timer value to .value
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with m.Else():
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m.d.sync += value.eq(self.csr.r.load.s)
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# If Timer allows updating value in memory, update
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m.d.comb += self.csr.r.current.set_val.eq(value)
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with m.If(self.csr.r.control.f.update_enable.s):
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m.d.sync += self.csr.r.current.set_stb.eq(1)
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with m.Else():
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m.d.sync += self.csr.r.current.set_stb.eq(0)
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return m
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