44 lines
1.2 KiB
Python
44 lines
1.2 KiB
Python
from nmigen import *
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from nmigen_soc import csr
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from nmigen.utils import *
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__all__ = ["GPIOOutput"]
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class GPIOOutput(Elaboratable):
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def __init__(self, gpio_out, *, bus_data_width, count=8, bus_granularity=None):
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self.gpio_out = gpio_out
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self.count = count
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bus_dw = bus_data_width
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if bus_granularity is None:
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bus_granularity = data_width
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bus_gr = bus_granularity
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with csr.Bank(name="gpio",
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addr_width=max(1, log2_int(-(-count//bus_gr), need_pow2=False)),
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data_width=bus_gr, type="mux") as self.csr:
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self.csr.r += [
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csr.Register(
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"switch", "rw", width=count,
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fields=[
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csr.Field("output_{}".format(i)) for i in range(count)
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]
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)
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]
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self.wb2csr = csr.WishboneCSRBridge(self.csr.mux.bus, data_width=bus_data_width)
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self.csr_bus = self.wb2csr.wb_bus
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def elaborate(self, platform):
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m = Module()
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m.submodules += self.csr, self.wb2csr
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m.d.comb += [
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self.gpio_out[i].eq(self.csr.r.switch.s[i])
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for i in range(self.count)
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]
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return m
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