160 lines
6.2 KiB
Python
160 lines
6.2 KiB
Python
from nmigen import *
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from nmigen_stdio.eth import rgmii
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from nmigen_soc import csr, wishbone
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from nmigen.utils import *
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from nmigen.lib.fifo import AsyncFIFO
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from nmigen.lib.cdc import FFSynchronizer, ResetSynchronizer
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__all__ = ["EthRGMIICore"]
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class EthRGMIICore(Elaboratable):
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def __init__(self, *, rx, tx, bus_data_width,
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rx_buffer_size=2**15, tx_buffer_size=2**15,
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bus_type="wishbone", bus_granularity=None, **kwargs):
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if not isinstance(rx, bool):
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raise TypeError("Must include either rx=True or False "
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"to indicate whether RX is used or not, not rx={}"
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.format(repr(rx)))
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self.rx = rx
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if not isinstance(tx, bool):
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raise TypeError("Must include either tx=True or False "
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"to indicate whether TX is used or not, not tx={}"
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.format(repr(tx)))
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self.tx = tx
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if bus_data_width < 9:
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raise ValueError("Bus data width must be at least 10, not {}"
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.format(bus_data_width))
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if bus_type not in ["wishbone"]:
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raise ValueError("Bus type must be "
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"\"wishbone\", not {}".format(bus_type))
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self.bus_type = bus_type
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if bus_type == "wishbone":
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self.rxdat_bus = wishbone.Interface(
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addr_width=0,
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data_width=bus_data_width,
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granularity=bus_granularity,
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**kwargs
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)
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if rx:
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self.rx_buffer_size = rx_buffer_size
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self.rx_stb = Signal()
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self.rx_eop = Signal()
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self.rx_io = rgmii.EthRGMIIRX(clk_domain="eth_rx")
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if tx:
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self.tx_buffer_size = tx_buffer_size
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self.tx_stb = Signal()
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self.tx_eop = Signal()
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self.tx_io = rgmii.EthRGMIITX(clk_domain="eth_tx")
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bus_dw = bus_data_width
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if bus_granularity is None:
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bus_granularity = data_width
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bus_gr = bus_granularity
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with csr.Bank(name="eth", addr_width=max(1, log2_int(bus_dw//bus_gr)),
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data_width=bus_gr, type="mux") as self.csr:
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self.csr.r += csr.Register("flags", "rw", width=bus_dw)
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with self.csr.r.flags as reg:
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if rx:
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reg.f += [
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csr.Field("rx_ready", "r", startbit=0, reset_value=1),
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csr.Field("rx_clear", "rw", startbit=8),
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]
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if tx:
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reg += [
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csr.Field("tx_ready", "r", startbit=4, reset_value=1),
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csr.Field("tx_send", "rw", startbit=12)
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]
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self.wb2csr = csr.WishboneCSRBridge(self.csr.mux.bus, data_width=bus_data_width)
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self.csr_bus = self.wb2csr.wb_bus
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def elaborate(self, platform):
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m = Module()
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if self.rx:
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m.submodules.rx = rx = self.rx_io
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if self.tx:
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m.submodules.tx = tx = self.tx_io
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m.submodules += self.csr, self.wb2csr
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###########
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# RX
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if self.rx:
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# RX FIFO ([7:0]=data ; [8]=is eop?)
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rx_fifo = AsyncFIFO(width=9, depth=self.rx_buffer_size)
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m.submodules += DomainRenamer({"write": "eth_rx", "read": "sync"})(rx_fifo)
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rx_clearing = Signal()
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m.d.comb += [
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# Write to FIFO
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# RX stops when clearing buffer
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rx_fifo.w_en.eq(rx.source.stb & ~rx_clearing),
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rx_fifo.w_data.eq(Cat(rx.source.payload.data, rx.source.eop)),
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]
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if self.bus_type == "wishbone":
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# Reading while clearing buffer would return invalid data
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with m.If(~rx_clearing):
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rxdat_r_en = Signal()
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m.d.comb += [
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rxdat_r_en.eq(self.rxdat_bus.cyc & self.rxdat_bus.stb & ~self.rxdat_bus.we &
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~self.rxdat_bus.ack & rx_fifo.r_rdy)
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]
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# Read from FIFO
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m.d.sync += rx_fifo.r_en.eq(rxdat_r_en)
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with m.If(self.rxdat_bus.sel[0] & rxdat_r_en):
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m.d.sync += self.rxdat_bus.dat_r.eq(rx_fifo.r_data)
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with m.Else():
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m.d.sync += self.rxdat_bus.dat_r.eq(Cat(Repl(0, 9), 1)) # [9]=no data?
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# RX data bus ACK
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with m.If(self.rxdat_bus.cyc & self.rxdat_bus.stb & ~self.rxdat_bus.we):
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m.d.sync += self.rxdat_bus.ack.eq(1)
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with m.If(self.rxdat_bus.ack):
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m.d.sync += self.rxdat_bus.ack.eq(0)
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# CSR - Buffer is ready
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# Set to 0 once buffer is full
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# Resets to 1 only when buffer has been completely cleared
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rx_ready_prev = Signal(reset=1)
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m.d.comb += self.csr.r.flags.f.rx_ready.set_stb.eq(1)
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with m.If(~rx_fifo.w_rdy):
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m.d.comb += self.csr.r.flags.f.rx_ready.set_val.eq(0)
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m.d.sync += rx_ready_prev.eq(0)
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with m.Else():
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m.d.comb += self.csr.r.flags.f.rx_ready.set_val.eq(rx_ready_prev)
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with m.If(~rx_ready_prev & ~rx_fifo.r_rdy):
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m.d.sync += rx_ready_prev.eq(1)
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# CSR - Buffer clearing
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# Starts clearing after flag is set to 1
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# Ignores flag during clearing
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with m.If(self.csr.r.flags.f.rx_clear.s & ~rx_clearing & rx_fifo.r_rdy):
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m.d.sync += [
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rx_fifo.r_en.eq(1),
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rx_clearing.eq(1)
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]
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with m.If(rx_clearing & ~rx_fifo.r_rdy):
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m.d.sync += [
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rx_fifo.r_en.eq(0),
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rx_clearing.eq(0)
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]
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# Useful signals
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m.submodules += [
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FFSynchronizer(rx.source.stb, self.rx_stb),
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FFSynchronizer(rx.source.eop, self.rx_eop),
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]
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###########
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# TX
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if self.tx:
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raise NotImplementedError("TX logic has not been implemented")
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return m
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