98 lines
3.4 KiB
Python
98 lines
3.4 KiB
Python
import argparse
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import struct
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from nmigen import *
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from nmigen_boards.versa_ecp5 import VersaECP5Platform_USRMCLK
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from heavycomps.cores import *
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from heavycomps.cfgs.ecp5 import *
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from minerva.core import Minerva
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from nmigen_soc import wishbone
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from nmigen.utils import *
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class Top(Elaboratable):
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def __init__(self, firmware):
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self.firmware = firmware
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def elaborate(self, platform):
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m = Module()
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# Referring to simplesoc_ecp5.py
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cd_sync = ClockDomain()
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m.domains += cd_sync
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m.d.comb += cd_sync.clk.eq(platform.request("clk100").i)
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io_user_led = [platform.request("led", i).o for i in range(8)]
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io_uart = platform.request("uart")
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io_spiflash = platform.request("spi_flash_1x")
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io_eth = platform.request("eth_rgmii", number=0)
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# FIXME: Without an sync stmt, clk100 must be checked...
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dummy = Signal()
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m.d.sync += dummy.eq(0)
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m.submodules.cpu = cpu = Minerva(with_icache=False, with_dcache=False, with_muldiv=False)
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m.submodules.ram = ram = wishbone.SRAM(Memory(width=32, depth=2**15, init=self.firmware),
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granularity=8, features={"err","cti","bte"})
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m.submodules.timer = timer = TimerCore(width=32,
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bus_data_width=32, bus_granularity=8)
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m.submodules.led = led = GPIOOutput(io_user_led, count=8,
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bus_data_width=32, bus_granularity=8)
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m.submodules.uart = uart = UARTCore(io_uart, sys_clk_freq=100e6,
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bus_data_width=32, bus_granularity=8)
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m.submodules.spi = spi = SPIFlashCore(io_spiflash, spi_protocol="standard", read_type="slow",
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addr_width=24, sys_clk_freq=100e6, freq=10e6,
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data_width=32, granularity=8)
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m.submodules += SPIFlashCoreCfg(spi)
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m.submodules.eth = eth = EthRGMIICore(rx=True, tx=False,
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bus_data_width=32, bus_granularity=8)
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m.submodules += EthRGMIICoreCfg(eth, io_eth, rx=True, tx=False)
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m.submodules.con = con = wishbone.InterconnectShared(
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addr_width=30, data_width=32, granularity=8,
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features={"err","cti","bte"},
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itors=[cpu.ibus, cpu.dbus],
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targets=[
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( ram.bus, 0x00000000 ),
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( uart.csr_bus, 0x02000000 ),
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( timer.csr_bus, 0x02000020 ),
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( led.csr_bus, 0x02000010 ),
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( spi.bus, 0x03000000 ),
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( spi.csr_bus, 0x02000100 ),
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( eth.csr_bus, 0x02000200 ),
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( eth.rxdat_bus, 0x02000204 )
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]
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)
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return m
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def read_firmware(file):
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firmware = []
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with open(file, "rb") as f:
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while True:
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word = f.read(4)
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if len(word) < 4:
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break
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firmware.append(struct.unpack("<I", word)[0])
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return firmware
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def main():
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parser = argparse.ArgumentParser()
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parser.add_argument("firmware_bin")
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parser.add_argument("build_dir")
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args = parser.parse_args()
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firmware = read_firmware(args.firmware_bin)
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top = Top(firmware)
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VersaECP5Platform_USRMCLK().build(top, build_dir=args.build_dir)
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if __name__ == "__main__":
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main()
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