100 lines
3.0 KiB
Python
100 lines
3.0 KiB
Python
import os
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import argparse
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import struct
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from nmigen import *
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from nmigen.back import pysim
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from nmigen_boards.versa_ecp5 import VersaECP5Platform
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from heavycomps import uart, wishbone
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from minerva.core import Minerva
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class SimpleWishboneSerial(Elaboratable):
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def __init__(self, tx, sys_clk_freq, baudrate=115200):
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self.tx = tx
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self.bus = wishbone.Interface()
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self.ftw = round(2**32*baudrate/sys_clk_freq)
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def elaborate(self, platform):
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m = Module()
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m.submodules.tx = tx = uart.RS232TX(self.ftw)
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m.d.comb += [
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tx.stb.eq(self.bus.cyc & self.bus.stb & self.bus.we),
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tx.data.eq(self.bus.dat_w),
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self.bus.ack.eq(tx.ack),
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self.tx.eq(tx.tx)
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]
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return m
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class Top(Elaboratable):
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def __init__(self, firmware, simulate):
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self.firmware = firmware
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self.simulate = simulate
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def elaborate(self, platform):
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m = Module()
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if self.simulate:
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io_user_led = Signal()
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io_uart_tx = Signal()
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else:
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cd_sync = ClockDomain(reset_less=True)
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m.domains += cd_sync
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m.d.comb += cd_sync.clk.eq(platform.request("clk100").i)
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io_user_led = platform.request("user_led").o
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io_uart_tx = platform.request("uart").tx.o
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counter = Signal(27)
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m.d.sync += counter.eq(counter + 1)
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m.d.comb += io_user_led.eq(counter[-1])
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m.submodules.cpu = cpu = Minerva(with_icache=False, with_dcache=False, with_muldiv=False)
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m.submodules.ram = ram = wishbone.SRAM(Memory(32, 1024, init=self.firmware))
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m.submodules.uart = uart = SimpleWishboneSerial(io_uart_tx, 100e6)
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m.submodules.con = con = wishbone.InterconnectShared(
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[cpu.ibus, cpu.dbus],
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[
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(lambda a: ~a[20], ram.bus),
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(lambda a: a[20], uart.bus)
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], register=True)
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return m
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def read_firmware(file):
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firmware = []
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with open(file, "rb") as f:
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while True:
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word = f.read(4)
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if len(word) < 4:
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break
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firmware.append(struct.unpack("<I", word)[0])
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return firmware
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def main():
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parser = argparse.ArgumentParser()
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parser.add_argument("--simulate", action="store_true")
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parser.add_argument("firmware_bin")
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parser.add_argument("build_dir")
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args = parser.parse_args()
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firmware = read_firmware(args.firmware_bin)
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top = Top(firmware, args.simulate)
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if args.simulate:
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os.makedirs(args.build_dir, exist_ok=True)
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with pysim.Simulator(top,
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vcd_file=open(os.path.join(args.build_dir, "simplesoc.vcd"), "w"),
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gtkw_file=open(os.path.join(args.build_dir, "simplesoc.gtkw"), "w")) as sim:
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sim.add_clock(1e-6)
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sim.run_until(1000e-6, run_passive=True)
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else:
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VersaECP5Platform().build(top, build_dir=args.build_dir)
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if __name__ == "__main__":
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main()
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