Next-generation FPGA SoC toolkit
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self: super:
rec {
yosys = super.yosys.overrideAttrs(oa: rec {
name = "yosys-${version}";
version = "2019-07-27";
srcs = [
(super.fetchFromGitHub {
owner = "yosyshq";
repo = "yosys";
rev = "6538671c84a12114a991d59569eede3e0d368758";
sha256 = "1l6v94a9vh9krmfsmd3v8l8xciwf028xvg93qf80s8a75djm7bc3";
name = "yosys";
})
# NOTE: the version of abc used here is synchronized with
# the one in the yosys Makefile of the version above;
# keep them the same for quality purposes.
(super.fetchFromGitHub {
owner = "berkeley-abc";
repo = "abc";
rev = "5776ad07e7247993976bffed4802a5737c456782";
sha256 = "1la4idmssg44rp6hd63sd5vybvs3vr14yzvwcg03ls37p39cslnl";
name = "yosys-abc";
})
];
buildInputs = oa.buildInputs ++ [ super.zlib ];
});
nextpnr = super.nextpnr.overrideAttrs(oa: rec {
name = "nextpnr-${version}";
version = "2019-07-22";
src = super.fetchFromGitHub {
owner = "yosyshq";
repo = "nextpnr";
rev = "ba050c21b94e816f9dd69f69b23ad5105858f401";
sha256 = "1wxsv1lcbi6bvv5vryvjz9mj530iva85wh6b6pvnfff2i4yc3p9q";
};
buildInputs = oa.buildInputs ++ [ super.eigen ];
cmakeFlags = oa.cmakeFlags ++ [ "-DUSE_OPENMP=ON" ];
});
icestorm = super.icestorm.overrideAttrs(oa: rec {
name = "icestorm-${version}";
version = "2019-07-03";
src = super.fetchFromGitHub {
owner = "cliffordwolf";
repo = "icestorm";
rev = "792cef084a751e32f541332feb4905f8e49e9943";
sha256 = "115qmgcz5ndw4z8ivk1cdlz6i2dzhq195gr8y4fjrjcb5jlacz23";
};
});
trellis = super.trellis.overrideAttrs(oa: rec {
name = "trellis-${version}";
version = "2019-07-18";
srcs = [
(super.fetchFromGitHub {
owner = "symbiflow";
repo = "prjtrellis";
rev = "b27c0da5d20a4c105fe9be2b5f8d859316613f44";
sha256 = "12jcs64agv5yhqq4zwjp2vd9y248608hz1gj187g1cfqrv0yc8d5";
name = "trellis";
})
(super.fetchFromGitHub {
owner = "symbiflow";
repo = "prjtrellis-db";
rev = "b4d626b6402c131e9a035470ffe4cf33ccbe7986";
sha256 = "0k26lq6c049ja8hhqcljwjb1y5k4gcici23l2n86gyp83jr03ilx";
name = "database";
})
];
});
llvm_7 = super.llvm_7.overrideAttrs(oa: {
name = oa.name + "-riscv";
cmakeFlags = oa.cmakeFlags ++ ["-DLLVM_EXPERIMENTAL_TARGETS_TO_BUILD=RISCV"];
});
rustc = super.rustc.overrideAttrs(oa: {
patches = oa.patches ++ [ ./compilers/rustc-riscv32i.patch ];
});
rustPlatform = super.makeRustPlatform { inherit rustc; inherit (super) cargo; };
}