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Next-generation FPGA SoC toolkit
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Sebastien Bourdeauducq 12032433ed use nixpkgs 19.03 
* too much breakage on nixos-unstable
* we should track upstream yosys/nextpnr more closely than nixpkgs does
 		2019-07-29 14:58:46 +08:00
compilers use nixpkgs 19.03 2019-07-29 14:58:46 +08:00
cores add experimental LiteDRAM package 2019-06-13 09:36:12 +08:00
eda nmigen: fix hash 2019-07-24 15:50:54 +08:00
examples use nmigen build system, upstream yosys, reorganize 2019-07-03 18:51:54 +08:00
firmware firmware: prevent Nix from corrupting output ELF 2019-07-29 13:58:21 +08:00
heavycomps add wishbone components 2019-05-02 12:53:08 +08:00
.gitignore add nix-build results to .gitignore 2019-03-25 23:36:52 +08:00
README.md use nixpkgs 19.03 2019-07-29 14:58:46 +08:00
default.nix use nmigen build system, upstream yosys, reorganize 2019-07-03 18:51:54 +08:00
heavycomps.nix add component library with UART 2019-03-19 16:52:02 +08:00
overlay.nix use nixpkgs 19.03 2019-07-29 14:58:46 +08:00
release.nix use nixpkgs 19.03 2019-07-29 14:58:46 +08:00

README.md

HeavyX

A FPGA SoC framework embracing cutting-edge open source technologies (nMigen, Yosys, SymbiFlow, Minerva, Nix, Rust).

This is work in progress!

"Hello World" SoC demo

Softcore system-on-chip on the Lattice ECP5 Versa board, built with a 100% Verilog/VHDL-free and 100% open source toolchain.

  • Everything written in nMigen (https://github.com/m-labs/nmigen/).
  • RISC-V 32-bit pipelined core (Minerva by Lambdaconcept).
  • 100MHz clock frequency.
  • Runs a Rust "hello world" program.

Use nixpkgs 19.03. If you are unfamiliar with Nix and just installed it on another (non-NixOS) distribution, simply run:

$ nix-channel --remove nixpkgs
$ nix-channel --add https://nixos.org/channels/nixos-19.03 nixpkgs
$ nix-channel --update

Optional: set up the M-Labs key and binary substituter for Nix (otherwise Nix will recompile LLVM, rustc, etc. on your machine). Create the file ~/.config/nix/nix.conf with the following contents:

substituters = https://cache.nixos.org https://nixbld.m-labs.hk
trusted-public-keys = cache.nixos.org-1:6NCHdD59X431o0gWypbMrAURkbJ16ZPMQFGspcDShjY= nixbld.m-labs.hk-1:5aSRVA5b320xbNvu30tqxVPXpld73bhtOeH6uAjRyHc=

Run nix-build -A simplesoc_ecp5 release.nix

You can also build manually and use your distribution's packages, but YMMV.

Bypass the ispCLOCK device using the jumpers on your board.

Create a versa.cfg file with:

interface ftdi
ftdi_vid_pid 0x0403 0x6010
ftdi_channel 0
ftdi_layout_init 0xfff8 0xfffb
reset_config none
adapter_khz 5000
jtag newtap ecp5 tap -irlen 8 -expected-id 0x01112043

Load the bitstream openocd -f versa.cfg -c "transport select jtag; init; svf result/top.svf; exit".

Watch the UART output at 115200bps.

Questions, comments: https://forum.m-labs.hk/ or IRC #m-labs on Freenode.