Next-generation FPGA SoC toolkit
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self: super:
{
llvm_7 = super.llvm_7.overrideAttrs(oa: {
name = oa.name + "-riscv";
cmakeFlags = oa.cmakeFlags ++ ["-DLLVM_EXPERIMENTAL_TARGETS_TO_BUILD=RISCV"];
});
rustc = super.rustc.overrideAttrs(oa: {
patches = oa.patches ++ [ ./compilers/rustc-riscv32i.patch ];
});
}