Next-generation FPGA SoC toolkit
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1.5 KiB

import argparse
from nmigen import *
from nmigen_boards.versa_ecp5 import VersaECP5Platform
from heavycomps import uart
class Top(Elaboratable):
def __init__(self, baudrate=115200):
self.baudrate = baudrate
def elaborate(self, platform):
m = Module()
cd_sync = ClockDomain(reset_less=True)
m.domains += cd_sync
m.d.comb += cd_sync.clk.eq(platform.request("clk100").i)
string = "Hello World!\r\n"
mem = Memory(width=8, depth=len(string),
init=[ord(c) for c in string])
m.submodules.rdport = rdport = mem.read_port(domain="comb")
wait = Signal()
tx = uart.RS232TX(round(2**32*self.baudrate/100e6))
m.submodules.tx = tx
m.d.comb += [
tx.stb.eq(~wait),
tx.data.eq(rdport.data),
platform.request("uart").tx.o.eq(tx.tx)
]
release = Signal()
counter = Signal(25)
m.d.sync += Cat(counter, release).eq(counter + 1)
with m.If(release):
m.d.sync += wait.eq(0)
with m.If(~wait & tx.ack):
with m.If(rdport.addr == len(string) - 1):
m.d.sync += rdport.addr.eq(0)
m.d.sync += wait.eq(1)
with m.Else():
m.d.sync += rdport.addr.eq(rdport.addr + 1)
return m
def main():
parser = argparse.ArgumentParser()
parser.add_argument("build_dir")
args = parser.parse_args()
VersaECP5Platform().build(Top(), build_dir=args.build_dir)
if __name__ == "__main__":
main()