import os import argparse import struct from nmigen import * from nmigen.back import pysim from nmigen_boards.versa_ecp5 import VersaECP5Platform from heavycomps import uart, wishbone from minerva.core import Minerva class SimpleWishboneSerial(Elaboratable): def __init__(self, tx, sys_clk_freq, baudrate=115200): self.tx = tx self.bus = wishbone.Interface() self.ftw = round(2**32*baudrate/sys_clk_freq) def elaborate(self, platform): m = Module() m.submodules.tx = tx = uart.RS232TX(self.ftw) m.d.comb += [ tx.stb.eq(self.bus.cyc & self.bus.stb & self.bus.we), tx.data.eq(self.bus.dat_w), self.bus.ack.eq(tx.ack), self.tx.eq(tx.tx) ] return m class Top(Elaboratable): def __init__(self, firmware, simulate): self.firmware = firmware self.simulate = simulate def elaborate(self, platform): m = Module() if self.simulate: io_user_led = Signal() io_uart_tx = Signal() else: cd_sync = ClockDomain(reset_less=True) m.domains += cd_sync m.d.comb += cd_sync.clk.eq(platform.request("clk100").i) io_user_led = platform.request("user_led").o io_uart_tx = platform.request("uart").tx.o counter = Signal(27) m.d.sync += counter.eq(counter + 1) m.d.comb += io_user_led.eq(counter[-1]) m.submodules.cpu = cpu = Minerva(with_icache=False, with_dcache=False, with_muldiv=False) m.submodules.ram = ram = wishbone.SRAM(Memory(32, 1024, init=self.firmware)) m.submodules.uart = uart = SimpleWishboneSerial(io_uart_tx, 100e6) m.submodules.con = con = wishbone.InterconnectShared( [cpu.ibus, cpu.dbus], [ (lambda a: ~a[20], ram.bus), (lambda a: a[20], uart.bus) ], register=True) return m def read_firmware(file): firmware = [] with open(file, "rb") as f: while True: word = f.read(4) if len(word) < 4: break firmware.append(struct.unpack("