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base: M-Labs:fd05fa560f816057e0e29aee094e039d36558d23
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M-Labs:core_lib
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compare: M-Labs:3598e08212a70534786e6da0aca9175955023830
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M-Labs:core_lib
M-Labs:master

2 Commits
fd05fa560f ... 3598e08212

Author SHA1 Message Date
Sebastien Bourdeauducq 3598e08212 symbiflow: 100MHz timing (HACK) 2019-06-09 00:06:17 +08:00
Sebastien Bourdeauducq d9b42a0807 clean up firmware compilation 2019-06-09 00:05:40 +08:00
3 changed files with 6 additions and 9 deletions
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4
eda/symbiflow.nix
View File

@ -7,8 +7,8 @@
buildPhase =
''
mkdir $out
${yosys}/bin/yosys -p "read_ilang $src/top.il; synth_ecp5 -top top -json $out/top.json"
${pkgs.nextpnr}/bin/nextpnr-ecp5 --json $out/top.json --textcfg $out/top.config `cat $src/device` --lpf $src/top.lpf
${yosys}/bin/yosys -p "read_ilang $src/top.il; synth_ecp5 -top top -nomux -json $out/top.json"
${pkgs.nextpnr}/bin/nextpnr-ecp5 --json $out/top.json --textcfg $out/top.config `cat $src/device` --lpf $src/top.lpf --freq 100
${pkgs.trellis}/bin/ecppack --svf-rowsize 100000 --svf $out/top.svf $out/top.config $out/top.bit
'';
};

8
firmware/default.nix
View File

@ -1,4 +1,4 @@
{ rustPlatform, rust-riscv32i-crates, binutils-riscv32, rustc, cargo }:
{ rustPlatform, rust-riscv32i-crates, binutils-riscv32 }:
rustPlatform.buildRustPackage rec {
name = "helloworld";
@ -7,14 +7,10 @@ rustPlatform.buildRustPackage rec {
src = ./.;
cargoSha256 = "0kf2pnfylfmzm0qvi4jfci43qvrnj1v5f037sb9zpvfqyddhdffl";
# HACK - rustc overlay does not update rustPlatform. Find out why.
configurePhase = ''echo XXX ${rustPlatform.rust.rustc} ${rustPlatform.rust.cargo}'';
buildPhase = ''
export CARGO_HOME=$(mktemp -d cargo-home.XXX)
export RUSTFLAGS="-L ${rust-riscv32i-crates}/lib/rustlib/riscv32i-unknown-none-elf/lib -C linker=${binutils-riscv32}/bin/riscv32-unknown-elf-ld -C link-arg=-Tlink.x"
export RUSTC=${rustc}/bin/rustc
${cargo}/bin/cargo build --release --target riscv32i-unknown-none-elf
cargo build --release --target riscv32i-unknown-none-elf
'';
doCheck = false;

3
overlay.nix
View File

@ -1,5 +1,5 @@
self: super:
{
rec {
llvm_7 = super.llvm_7.overrideAttrs(oa: {
name = oa.name + "-riscv";
cmakeFlags = oa.cmakeFlags ++ ["-DLLVM_EXPERIMENTAL_TARGETS_TO_BUILD=RISCV"];
@ -7,4 +7,5 @@ self: super:
rustc = super.rustc.overrideAttrs(oa: {
patches = oa.patches ++ [ ./compilers/rustc-riscv32i.patch ];
});
rustPlatform = super.makeRustPlatform { inherit rustc; inherit (super) cargo; };
}