cores/minerva.nix

@@ -6,8 +6,8 @@ python3Packages.buildPythonPackage {
   src = fetchFromGitHub {
     owner = "lambdaconcept";
     repo = "minerva";
-    rev = "eefcbd066f2144422b06b398b4651dbd86db52b6";
-    sha256 = "0kv5sgyggic90hf4s3xf2aanwqn1961zhvng6hhzmjsqn1m17rdq";
+    rev = "2a017224497d50505395b4d9e09ab74412ccd131";
+    sha256 = "1bc0phlmxhcw15d1b23xgrsazgxxxi2l1h3mvk7zb68h5pgq4svm";
   };
 
   propagatedBuildInputs = [ nmigen jtagtap ];

default.nix

@@ -19,7 +19,7 @@ rec {
     binutils-riscv = pkgs.callPackage ./compilers/binutils.nix { platform = "riscv32"; };
     rust-riscv32imc-crates = pkgs.callPackage ./compilers/rust-riscv32imc-crates.nix { };
 
-    fw-helloworld = pkgs.callPackage ./firmware { inherit rust-riscv32imc-crates binutils-riscv; };
+    helloworld = pkgs.callPackage ./firmware { inherit rust-riscv32imc-crates binutils-riscv; };
   };
   lib = {
     symbiflow = import ./eda/symbiflow.nix { inherit pkgs; inherit (drvs) yosys; };

eda/nmigen.nix

@@ -6,13 +6,13 @@ python3Packages.buildPythonPackage {
   src = fetchFromGitHub {
     owner = "m-labs";
     repo = "nmigen";
-    rev = "b45c5119f573e156a3aad4a362ca210d6e40505e";
-    sha256 = "1qyh6h8amqz9z6l2h0rj4lzpkm1i2fgbxn5m0p6igwflqk0svffz";
+    rev = "c337246fc581ccac0273f5661f65815266144862";
+    sha256 = "03gbd5k87w9ifa8iz0wprpswv7qn93swzcvjnvs5czn39lwvwgh4";
   };
 
   checkPhase = "PATH=${yosys}/bin:${symbiyosys}/bin:${yices}/bin:$PATH python -m unittest discover nmigen.test -v";
 
-  propagatedBuildInputs = [ python3Packages.bitarray python3Packages.pyvcd python3Packages.jinja2 ];
+  propagatedBuildInputs = [ python3Packages.bitarray python3Packages.pyvcd ];
 
   meta = with stdenv.lib; {
     description = "A refreshed Python toolbox for building complex digital hardware";

examples/simplesoc_ecp5.nix

@@ -7,7 +7,7 @@ let
     ''
     mkdir $out
 
-    python ${./simplesoc_ecp5.py} ${hx.drvs.fw-helloworld}/helloworld.bin $out/top.il
+    python ${./simplesoc_ecp5.py} > $out/top.il
 
     cat > $out/top.lpf << EOF
     LOCATE COMP "clk100" SITE "P3";

examples/simplesoc_ecp5.py

@@ -1,6 +1,3 @@
-import argparse
-import struct
-
 from nmigen import *
 from nmigen.back import rtlil
 
@@ -27,10 +24,9 @@ class SimpleWishboneSerial(Elaboratable):
         
 
 class Top(Elaboratable):
-    def __init__(self, firmware):
+    def __init__(self):
         self.clk100 = Signal()
         self.serial_tx = Signal()
-        self.firmware = firmware
 
     def elaborate(self, platform):
         m = Module()
@@ -40,7 +36,7 @@ class Top(Elaboratable):
         m.d.comb += cd_sync.clk.eq(self.clk100)
 
         m.submodules.cpu = cpu = Minerva(with_icache=False, with_dcache=False, with_muldiv=False)
-        m.submodules.ram = ram = wishbone.SRAM(Memory(32, 1024, init=self.firmware))
+        m.submodules.ram = ram = wishbone.SRAM(Memory(32, 1024))
         m.submodules.uart = uart = SimpleWishboneSerial(self.serial_tx, 100e6)
         m.submodules.con = con = wishbone.InterconnectShared(
             [cpu.ibus, cpu.dbus],
@@ -52,30 +48,11 @@ class Top(Elaboratable):
         return m
 
 
-def read_firmware(file):
-    firmware = []
-    with open(file, "rb") as f:
-        while True:
-            word = f.read(4)
-            if len(word) < 4:
-                break
-            firmware.append(struct.unpack(">I", word)[0])
-    return firmware
-
-
 def main():
-    parser = argparse.ArgumentParser()
-    parser.add_argument("firmware_bin")
-    parser.add_argument("output_file")
-    args = parser.parse_args()
-
-    firmware = read_firmware(args.firmware_bin)
-
-    top = Top(firmware)
+    top = Top()
     output = rtlil.convert(Fragment.get(top, None),
         ports=(top.clk100, top.serial_tx))
-    with open(args.output_file, "w") as f:
-        f.write(output)
+    print(output)
 
 if __name__ == "__main__":
     main()