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base: M-Labs:83ffe66f707b8a5d7673c36034289c27a2e62b6f
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M-Labs:core_lib
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compare: M-Labs:ad4f00e93d44be4f59b4400afe727cf7473b96b0
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M-Labs:core_lib
M-Labs:master

No commits in common. "83ffe66f707b8a5d7673c36034289c27a2e62b6f" and "ad4f00e93d44be4f59b4400afe727cf7473b96b0" have entirely different histories.
83ffe66f70 ... ad4f00e93d

4 changed files with 4 additions and 11 deletions
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2
examples/simplesoc_ecp5.nix
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@ -14,8 +14,6 @@ let
IOBUF PORT "clk100" IO_TYPE=LVDS; IOBUF PORT "clk100" IO_TYPE=LVDS;
LOCATE COMP "serial_tx" SITE "A11"; LOCATE COMP "serial_tx" SITE "A11";
IOBUF PORT "serial_tx" IO_TYPE=LVCMOS33; IOBUF PORT "serial_tx" IO_TYPE=LVCMOS33;
LOCATE COMP "led" SITE "E16";
IOBUF PORT "led" IO_TYPE=LVCMOS25;
EOF EOF
echo -n "--um-45k --speed 8 --package CABGA381" > $out/device echo -n "--um-45k --speed 8 --package CABGA381" > $out/device

7
examples/simplesoc_ecp5.py
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@ -29,7 +29,6 @@ class SimpleWishboneSerial(Elaboratable):
class Top(Elaboratable): class Top(Elaboratable):
def __init__(self, firmware): def __init__(self, firmware):
self.clk100 = Signal() self.clk100 = Signal()
self.led = Signal()
self.serial_tx = Signal() self.serial_tx = Signal()
self.firmware = firmware self.firmware = firmware
@ -40,10 +39,6 @@ class Top(Elaboratable):
m.domains += cd_sync m.domains += cd_sync
m.d.comb += cd_sync.clk.eq(self.clk100) m.d.comb += cd_sync.clk.eq(self.clk100)
counter = Signal(27)
m.d.sync += counter.eq(counter + 1)
m.d.comb += self.led.eq(counter[-1])
m.submodules.cpu = cpu = Minerva(with_icache=False, with_dcache=False, with_muldiv=False) m.submodules.cpu = cpu = Minerva(with_icache=False, with_dcache=False, with_muldiv=False)
m.submodules.ram = ram = wishbone.SRAM(Memory(32, 1024, init=self.firmware)) m.submodules.ram = ram = wishbone.SRAM(Memory(32, 1024, init=self.firmware))
m.submodules.uart = uart = SimpleWishboneSerial(self.serial_tx, 100e6) m.submodules.uart = uart = SimpleWishboneSerial(self.serial_tx, 100e6)
@ -78,7 +73,7 @@ def main():
top = Top(firmware) top = Top(firmware)
output = rtlil.convert(Fragment.get(top, None), output = rtlil.convert(Fragment.get(top, None),
ports=(top.clk100, top.led, top.serial_tx)) ports=(top.clk100, top.serial_tx))
with open(args.output_file, "w") as f: with open(args.output_file, "w") as f:
f.write(output) f.write(output)

4
firmware/memory.x
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@ -1,5 +1,5 @@
MEMORY MEMORY
{ {
FLASH : ORIGIN = 0x00000000, LENGTH = 16K FLASH : ORIGIN = 0x80000000, LENGTH = 16M
RAM : ORIGIN = 0x0004000, LENGTH = 16K RAM : ORIGIN = 0x81000000, LENGTH = 16K
} }

2
firmware/src/main.rs
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@ -11,7 +11,7 @@ fn main() -> ! {
let foo = "hello world\n"; let foo = "hello world\n";
loop { loop {
for c in foo.chars() { for c in foo.chars() {
let mem = 0x00400000 as *mut u8; let mem = 0x1001_3000 as *mut u8;
unsafe { *mem = c as u8 } unsafe { *mem = c as u8 }
} }
} }