reinstate riscv32i

compilers/rustc-riscv32i.patch

@@ -0,0 +1,67 @@
+commit 23c32a1597df69083f4fa6fb932410cb342e266e
+Author: Sebastien Bourdeauducq <sb@m-labs.hk>
+Date:   Tue Apr 9 00:15:31 2019 +0800
+
+    add riscv32i
+
+diff --git a/src/librustc_target/spec/mod.rs b/src/librustc_target/spec/mod.rs
+index 46fefd78f4..181342db7d 100644
+--- a/src/librustc_target/spec/mod.rs
++++ b/src/librustc_target/spec/mod.rs
+@@ -465,6 +465,7 @@ supported_targets! {
+     ("aarch64-unknown-hermit", aarch64_unknown_hermit),
+     ("x86_64-unknown-hermit", x86_64_unknown_hermit),
+ 
++    ("riscv32i-unknown-none-elf", riscv32i_unknown_none_elf),
+     ("riscv32imc-unknown-none-elf", riscv32imc_unknown_none_elf),
+     ("riscv32imac-unknown-none-elf", riscv32imac_unknown_none_elf),
+     ("riscv64imac-unknown-none-elf", riscv64imac_unknown_none_elf),
+diff --git a/src/librustc_target/spec/riscv32i_unknown_none_elf.rs b/src/librustc_target/spec/riscv32i_unknown_none_elf.rs
+new file mode 100644
+index 0000000000..a015e16d93
+--- /dev/null
++++ b/src/librustc_target/spec/riscv32i_unknown_none_elf.rs
+@@ -0,0 +1,31 @@
++use crate::spec::{LinkerFlavor, LldFlavor, PanicStrategy,
++           Target, TargetOptions, TargetResult};
++
++pub fn target() -> TargetResult {
++    Ok(Target {
++        data_layout: "e-m:e-p:32:32-i64:64-n32-S128".to_string(),
++        llvm_target: "riscv32".to_string(),
++        target_endian: "little".to_string(),
++        target_pointer_width: "32".to_string(),
++        target_c_int_width: "32".to_string(),
++        target_os: "none".to_string(),
++        target_env: String::new(),
++        target_vendor: "unknown".to_string(),
++        arch: "riscv32".to_string(),
++        linker_flavor: LinkerFlavor::Lld(LldFlavor::Ld),
++
++        options: TargetOptions {
++            linker: Some("rust-lld".to_string()),
++            cpu: "generic-rv32".to_string(),
++            max_atomic_width: Some(32),
++            atomic_cas: true,
++            features: "-m,-a,-c".to_string(),
++            executables: true,
++            panic_strategy: PanicStrategy::Abort,
++            relocation_model: "static".to_string(),
++            emit_debug_gdb_scripts: false,
++            abi_blacklist: super::riscv_base::abi_blacklist(),
++            .. Default::default()
++        },
++    })
++}
+diff --git a/src/tools/build-manifest/src/main.rs b/src/tools/build-manifest/src/main.rs
+index 61cc78ad80..4364ef41f9 100644
+--- a/src/tools/build-manifest/src/main.rs
++++ b/src/tools/build-manifest/src/main.rs
+@@ -92,6 +92,7 @@ static TARGETS: &[&str] = &[
+     "powerpc-unknown-linux-gnu",
+     "powerpc64-unknown-linux-gnu",
+     "powerpc64le-unknown-linux-gnu",
++    "riscv32i-unknown-none-elf",
+     "riscv32imc-unknown-none-elf",
+     "riscv32imac-unknown-none-elf",
+     "riscv64imac-unknown-none-elf",

examples/simplesoc_ecp5.py

@@ -2,7 +2,7 @@ import argparse
 import struct
 
 from nmigen import *
-from nmigen.back import rtlil
+from nmigen.back import rtlil, pysim
 
 from heavycomps import uart, wishbone
 from minerva.core import Minerva
@@ -27,8 +27,9 @@ class SimpleWishboneSerial(Elaboratable):
         
 
 class Top(Elaboratable):
-    def __init__(self, firmware):
+    def __init__(self, firmware, create_clock):
-        self.clk100 = Signal()
+        if create_clock:
+            self.clk100 = Signal()
         self.led = Signal()
         self.serial_tx = Signal()
         self.firmware = firmware
@@ -36,9 +37,10 @@ class Top(Elaboratable):
     def elaborate(self, platform):
         m = Module()
 
-        cd_sync = ClockDomain(reset_less=True)
+        if hasattr(self, "clk100"):
-        m.domains += cd_sync
+            cd_sync = ClockDomain(reset_less=True)
-        m.d.comb += cd_sync.clk.eq(self.clk100)
+            m.domains += cd_sync
+            m.d.comb += cd_sync.clk.eq(self.clk100)
 
         counter = Signal(27)
         m.d.sync += counter.eq(counter + 1)
@@ -64,23 +66,31 @@ def read_firmware(file):
             word = f.read(4)
             if len(word) < 4:
                 break
-            firmware.append(struct.unpack(">I", word)[0])
+            firmware.append(struct.unpack("<I", word)[0])
     return firmware
 
 
 def main():
     parser = argparse.ArgumentParser()
+    parser.add_argument("--simulate", action="store_true")
     parser.add_argument("firmware_bin")
     parser.add_argument("output_file")
     args = parser.parse_args()
 
     firmware = read_firmware(args.firmware_bin)
+    top = Top(firmware, create_clock=not args.simulate)
 
-    top = Top(firmware)
+    if args.simulate:
-    output = rtlil.convert(Fragment.get(top, None),
+        with pysim.Simulator(top,
-        ports=(top.clk100, top.led, top.serial_tx))
+                vcd_file=open(args.output_file + ".vcd", "w"),
-    with open(args.output_file, "w") as f:
+                gtkw_file=open(args.output_file + ".gtkw", "w")) as sim:
-        f.write(output)
+            sim.add_clock(1e-6)
+            sim.run_until(100e-6, run_passive=True)
+    else:
+        output = rtlil.convert(Fragment.get(top, None),
+            ports=(top.clk100, top.led, top.serial_tx))
+        with open(args.output_file, "w") as f:
+            f.write(output)
 
 if __name__ == "__main__":
     main()

overlay.nix

@@ -4,4 +4,7 @@ self: super:
     name = oa.name + "-riscv";
     cmakeFlags = oa.cmakeFlags ++ ["-DLLVM_EXPERIMENTAL_TARGETS_TO_BUILD=RISCV"];
   });
+  rustc = super.rustc.overrideAttrs(oa: {
+    patches = oa.patches ++ [ ./compilers/rustc-riscv32i.patch ];
+  });
 }