eda/vivado.nix

@@ -22,7 +22,7 @@ let
   };
 in
   {
-    buildBitstream = { name, src, vivadoPath ? "/opt/Xilinx/Vivado/2018.3" }:
+    buildBitstream = { name, src, vivadoPath ? "/home/sb/opt/Xilinx/Vivado/2018.3" }:
       pkgs.stdenv.mkDerivation {
         inherit name src;
         phases = [ "buildPhase" ];

examples/helloworld.nix

@@ -8,7 +8,7 @@ let
     ''
     mkdir $out
 
-    python ${./helloworld_kintex7.py} > $out/top.v
+    python ${./helloworld.py} > $out/top.v
 
     cat > $out/top.xdc << EOF
     set_property LOC K24 [get_ports serial_tx]

examples/helloworld.py

@@ -4,7 +4,7 @@ from nmigen.back import verilog
 from heavycomps import uart
 
 
-class Top(Elaboratable):
+class Top:
     def __init__(self, baudrate=115200):
         self.baudrate = baudrate
         self.clk156_p = Signal()

heavycomps/heavycomps/roundrobin.py

@@ -1,7 +1,7 @@
 from nmigen import *
 
 
-class RoundRobin(Elaboratable):
+class RoundRobin:
     def __init__(self, n):
         self.n = n
         self.request = Signal(n)

heavycomps/heavycomps/test/test_uart.py

@@ -6,7 +6,7 @@ from nmigen.back.pysim import *
 from heavycomps import uart
 
 
-class Loopback(Elaboratable):
+class Loopback:
     def __init__(self, tuning_word=2**31):
         self.tx = uart.RS232TX(tuning_word)
         self.rx = uart.RS232RX(tuning_word)

heavycomps/heavycomps/uart.py

@@ -2,7 +2,7 @@ from nmigen import *
 from nmigen.lib.cdc import MultiReg
 
 
-class RS232RX(Elaboratable):
+class RS232RX:
     def __init__(self, tuning_word):
         self.rx = Signal()
         self.data = Signal(8)
@@ -58,7 +58,7 @@ class RS232RX(Elaboratable):
         return value
 
 
-class RS232TX(Elaboratable):
+class RS232TX:
     def __init__(self, tuning_word):
         self.tx = Signal(reset=1)
         self.data = Signal(8)