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263b04245e
...
40eced0136
12
default.nix
12
default.nix
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@ -1,8 +1,4 @@
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{ pkgs }:
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let
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hx = import ./derivations.nix { inherit pkgs; };
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in
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hx // {
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symbiflow = import ./eda/symbiflow.nix { inherit pkgs; yosys = hx.yosys; };
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vivado = import ./eda/vivado.nix { inherit pkgs; };
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}
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{ pkgs ? import <nixpkgs> {}}:
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(import ./derivations.nix { inherit pkgs; }) // {
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vivado = import ./eda/vivado.nix { inherit pkgs; };
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}
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@ -1,15 +0,0 @@
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{ pkgs, yosys }:
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{
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buildBitstream = { name, src }:
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pkgs.stdenv.mkDerivation {
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inherit name src;
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phases = [ "buildPhase" ];
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buildPhase =
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''
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mkdir $out
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${yosys}/bin/yosys -p "read_ilang $src/top.il; synth_ecp5 -top top -json $out/top.json"
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${pkgs.nextpnr}/bin/nextpnr-ecp5 --json $out/top.json --textcfg $out/top.config `cat $src/device` --lpf $src/top.lpf
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${pkgs.trellis}/bin/ecppack --svf-rowsize 100000 --svf $out/top.svf $out/top.config $out/top.bit
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'';
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};
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}
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@ -33,5 +33,5 @@ in
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mkdir $out
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cp *.dcp *.rpt *.bit $out
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'';
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};
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};
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}
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@ -1,26 +0,0 @@
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{ pkgs ? import <nixpkgs> {}
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, hx ? import ../default.nix { inherit pkgs; }}:
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let
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symbiflowInput = pkgs.runCommand "helloworld-symbiflow-input" {
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buildInputs = [ (pkgs.python3.withPackages(ps: [hx.nmigen hx.heavycomps])) hx.yosys ];
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}
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''
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mkdir $out
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python ${./helloworld_ecp5.py} > $out/top.il
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cat > $out/top.lpf << EOF
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LOCATE COMP "serial_tx" SITE "A4";
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IOBUF PORT "P3" IO_TYPE=LVDS;
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LOCATE COMP "tx" SITE "B19";
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IOBUF PORT "C11" IO_TYPE=LVCMOS33;
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EOF
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echo -n "--um-45k --package CABGA381" > $out/device
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'';
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in
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hx.symbiflow.buildBitstream {
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name = "helloworld-bitstream";
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src = symbiflowInput;
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}
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@ -1,49 +0,0 @@
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from nmigen import *
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from nmigen.back import rtlil
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from heavycomps import uart
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class Top(Elaboratable):
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def __init__(self, baudrate=115200):
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self.baudrate = baudrate
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self.clk100 = Signal()
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self.serial_tx = Signal()
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def elaborate(self, platform):
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m = Module()
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cd_sync = ClockDomain(reset_less=True)
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m.domains += cd_sync
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m.d.comb += cd_sync.clk.eq(self.clk100)
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string = "Hello World!\r\n"
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mem = Memory(width=8, depth=len(string),
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init=[ord(c) for c in string])
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m.submodules.rdport = rdport = mem.read_port(synchronous=False)
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tx = uart.RS232TX(round(2**32*self.baudrate/100e6))
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m.submodules.tx = tx
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m.d.comb += [
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tx.stb.eq(1),
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tx.data.eq(rdport.data),
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self.serial_tx.eq(tx.tx)
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]
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with m.If(tx.ack):
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with m.If(rdport.addr == len(string) - 1):
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m.d.sync += rdport.addr.eq(0)
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with m.Else():
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m.d.sync += rdport.addr.eq(rdport.addr + 1)
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return m
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def main():
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top = Top()
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output = rtlil.convert(Fragment.get(top, None),
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ports=(top.clk100, top.serial_tx))
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print(output)
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if __name__ == "__main__":
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main()
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@ -2,7 +2,7 @@
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, hx ? import ../default.nix { inherit pkgs; }}:
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let
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vivadoInput = pkgs.runCommand "helloworld-vivado-input" {
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vivadoInput = pkgs.runCommand "test-vivado-input" {
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buildInputs = [ (pkgs.python3.withPackages(ps: [hx.nmigen hx.heavycomps])) hx.yosys ];
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}
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''
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@ -43,6 +43,6 @@ let
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'';
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in
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hx.vivado.buildBitstream {
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name = "helloworld-bitstream";
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name = "test-design";
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src = vivadoInput;
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}
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@ -1,9 +1,5 @@
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{ pkgs ? import <nixpkgs> {}}:
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let
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derivations = import ./derivations.nix { inherit pkgs; };
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jobs = derivations // {
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helloworld_ecp5 = import ./examples/helloworld_ecp5.nix { inherit pkgs; };
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helloworld_kintex7 = import ./examples/helloworld_kintex7.nix { inherit pkgs; };
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};
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in
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builtins.mapAttrs (name: value: pkgs.lib.hydraJob value) jobs
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builtins.mapAttrs (name: value: pkgs.lib.hydraJob value) derivations
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