diff --git a/heavycomps/heavycomps/uart.py b/heavycomps/heavycomps/uart.py
index abe80c0..6fb6f23 100644
--- a/heavycomps/heavycomps/uart.py
+++ b/heavycomps/heavycomps/uart.py
@@ -2,6 +2,9 @@ from nmigen import *
 from nmigen.lib.cdc import MultiReg
 
 
+__all__ = ["RS232RX", "RS232TX"]
+
+
 class RS232RX(Elaboratable):
     def __init__(self, tuning_word):
         self.rx = Signal()