From ca0707fa88b71959c3a2a56c0f4a31da27b1a61e Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Mon, 25 Mar 2019 16:50:01 +0800 Subject: [PATCH] print hello world on UART --- examples/{demo.nix => helloworld.nix} | 0 examples/{demo.py => helloworld.py} | 13 ++++++++++++- 2 files changed, 12 insertions(+), 1 deletion(-) rename examples/{demo.nix => helloworld.nix} (100%) rename examples/{demo.py => helloworld.py} (68%) diff --git a/examples/demo.nix b/examples/helloworld.nix similarity index 100% rename from examples/demo.nix rename to examples/helloworld.nix diff --git a/examples/demo.py b/examples/helloworld.py similarity index 68% rename from examples/demo.py rename to examples/helloworld.py index f2d9a8e..75ac1fc 100644 --- a/examples/demo.py +++ b/examples/helloworld.py @@ -20,13 +20,24 @@ class Top: m.submodules.clock = Instance("IBUFGDS", i_I=self.clk156_p, i_IB=self.clk156_n, o_O=cd_sync.clk) + string = "Hello World!\r\n" + mem = Memory(width=8, depth=len(string), + init=[ord(c) for c in string]) + m.submodules.rdport = rdport = mem.read_port(synchronous=False) + tx = uart.RS232TX(round(2**32*self.baudrate/self.clk_freq)) m.submodules.tx = tx m.d.comb += [ tx.stb.eq(1), - tx.data.eq(ord("A")), + tx.data.eq(rdport.data), self.serial_tx.eq(tx.tx) ] + + with m.If(tx.ack): + with m.If(rdport.addr == len(string) - 1): + m.d.sync += rdport.addr.eq(0) + with m.Else(): + m.d.sync += rdport.addr.eq(rdport.addr + 1) return m