diff --git a/examples/testing_ecp5.py b/examples/testing_ecp5.py
index 1c0822b..b355343 100644
--- a/examples/testing_ecp5.py
+++ b/examples/testing_ecp5.py
@@ -41,7 +41,7 @@ class Top(Elaboratable):
         m.submodules.timer = timer = TimerCore(width=32,
                                                bus_data_width=32, bus_granularity=8)
         m.submodules.led = led = GPIOOutput(io_user_led, count=8,
-                                            bus_data_width=32, bus_granularity=8)
+                                            bus_data_width=32, bus_granularity=8, invert=True)
         m.submodules.uart = uart = UARTCore(io_uart, sys_clk_freq=100e6,
                                             bus_data_width=32, bus_granularity=8)
         m.submodules.spi = spi = SPIFlashCore(io_spiflash, spi_protocol="standard", read_type="slow", 
diff --git a/heavycomps/heavycomps/cores/gpio.py b/heavycomps/heavycomps/cores/gpio.py
index a49b143..56ee41d 100644
--- a/heavycomps/heavycomps/cores/gpio.py
+++ b/heavycomps/heavycomps/cores/gpio.py
@@ -7,9 +7,10 @@ __all__ = ["GPIOOutput"]
 
 
 class GPIOOutput(Elaboratable):
-    def __init__(self, gpio_out, *, bus_data_width, count=8, bus_granularity=None):
+    def __init__(self, gpio_out, *, bus_data_width, count=8, bus_granularity=None, invert=False):
         self.gpio_out = gpio_out
         self.count = count
+        self.invert = 1 if invert else 0
 
         bus_dw = bus_data_width
         if bus_granularity is None:
@@ -17,16 +18,14 @@ class GPIOOutput(Elaboratable):
         bus_gr = bus_granularity
 
         with csr.Bank(name="gpio",
-                      addr_width=max(1, log2_int(-(-count//bus_gr), need_pow2=False)),
+                      addr_width=max(1, log2_int(-(-count//bus_gr), need_pow2=False)) + 1,
                       data_width=bus_gr, type="mux") as self.csr:
-            self.csr.r += [
-                csr.Register(
-                    "switch", "rw", width=count,
-                    fields=[
-                        csr.Field("output_{}".format(i)) for i in range(count)
-                    ]
-                )
-            ]
+            self.csr.r += csr.Register("switch", "rw", width=count)
+            with self.csr.r.switch as reg:
+                reg.f += [
+                    csr.Field("output_{}".format(i), reset_value=self.invert)
+                    for i in range(count)
+                ]
         self.wb2csr = csr.WishboneCSRBridge(self.csr.mux.bus, data_width=bus_data_width)
         self.csr_bus = self.wb2csr.wb_bus
 
@@ -36,7 +35,7 @@ class GPIOOutput(Elaboratable):
         m.submodules += self.csr, self.wb2csr
 
         m.d.comb += [
-            self.gpio_out[i].eq(self.csr.r.switch.s[i])
+            self.gpio_out[i].eq(self.csr.r.switch.s[i] ^ self.invert)
             for i in range(self.count)
         ]