From b2bcbd7048ed86d618073240eb99374b0495c0e0 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Mon, 25 Mar 2019 16:10:07 +0800 Subject: [PATCH] add UART example --- examples/demo.nix | 48 +++++++++++++++++++++++++++++++++++++++++++++++ examples/demo.py | 41 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 89 insertions(+) create mode 100644 examples/demo.nix create mode 100644 examples/demo.py diff --git a/examples/demo.nix b/examples/demo.nix new file mode 100644 index 0000000..c25d772 --- /dev/null +++ b/examples/demo.nix @@ -0,0 +1,48 @@ +{ pkgs ? import {} +, hx ? import ../default.nix { inherit pkgs; }}: + +let + vivadoInput = pkgs.runCommand "test-vivado-input" { + buildInputs = [ (pkgs.python3.withPackages(ps: [hx.nmigen hx.heavycomps])) hx.yosys ]; + } + '' + mkdir $out + + python ${./demo.py} > $out/top.v + + cat > $out/top.xdc << EOF + set_property LOC K24 [get_ports serial_tx] + set_property IOSTANDARD LVCMOS25 [get_ports serial_tx] + + set_property LOC K28 [get_ports clk156_p] + set_property IOSTANDARD LVDS_25 [get_ports clk156_p] + set_property DIFF_TERM TRUE [get_ports clk156_p] + + set_property LOC K29 [get_ports clk156_n] + set_property IOSTANDARD LVDS_25 [get_ports clk156_n] + set_property DIFF_TERM TRUE [get_ports clk156_n] + + create_clock -name clk156 -period 6.4 [get_nets clk156_p] + EOF + + cat > $out/top.tcl << EOF + create_project -force -name top -part xc7k325t-ffg900-2 + set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project] + add_files {top.v} + set_property library work [get_files {top.v}] + read_xdc top.xdc + synth_design -top top -part xc7k325t-ffg900-2 + opt_design + place_design + route_design + set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] + set_property BITSTREAM.GENERAL.COMPRESS True [current_design] + write_bitstream -force top.bit + quit + EOF + ''; +in + hx.vivado.buildBitstream { + name = "test-design"; + src = vivadoInput; + } diff --git a/examples/demo.py b/examples/demo.py new file mode 100644 index 0000000..f2d9a8e --- /dev/null +++ b/examples/demo.py @@ -0,0 +1,41 @@ +from nmigen import * +from nmigen.back import verilog + +from heavycomps import uart + + +class Top: + def __init__(self, clk_freq=156e6, baudrate=115200): + self.clk_freq = clk_freq + self.baudrate = baudrate + self.clk156_p = Signal() + self.clk156_n = Signal() + self.serial_tx = Signal() + + def elaborate(self, platform): + m = Module() + + cd_sync = ClockDomain(reset_less=True) + m.domains += cd_sync + m.submodules.clock = Instance("IBUFGDS", + i_I=self.clk156_p, i_IB=self.clk156_n, o_O=cd_sync.clk) + + tx = uart.RS232TX(round(2**32*self.baudrate/self.clk_freq)) + m.submodules.tx = tx + m.d.comb += [ + tx.stb.eq(1), + tx.data.eq(ord("A")), + self.serial_tx.eq(tx.tx) + ] + + return m + + +def main(): + top = Top() + output = verilog.convert(Fragment.get(top, None), + ports=(top.clk156_p, top.clk156_n, top.serial_tx)) + print(output) + +if __name__ == "__main__": + main()