diff --git a/examples/helloworld_kintex7.py b/examples/helloworld_kintex7.py
index 4d21506..198998d 100644
--- a/examples/helloworld_kintex7.py
+++ b/examples/helloworld_kintex7.py
@@ -4,7 +4,7 @@ from nmigen.back import verilog
 from heavycomps import uart
 
 
-class Top:
+class Top(Elaboratable):
     def __init__(self, baudrate=115200):
         self.baudrate = baudrate
         self.clk156_p = Signal()
diff --git a/heavycomps/heavycomps/roundrobin.py b/heavycomps/heavycomps/roundrobin.py
index 5747884..5963345 100644
--- a/heavycomps/heavycomps/roundrobin.py
+++ b/heavycomps/heavycomps/roundrobin.py
@@ -1,7 +1,7 @@
 from nmigen import *
 
 
-class RoundRobin:
+class RoundRobin(Elaboratable):
     def __init__(self, n):
         self.n = n
         self.request = Signal(n)
diff --git a/heavycomps/heavycomps/test/test_uart.py b/heavycomps/heavycomps/test/test_uart.py
index 0177fd2..fb127e6 100644
--- a/heavycomps/heavycomps/test/test_uart.py
+++ b/heavycomps/heavycomps/test/test_uart.py
@@ -6,7 +6,7 @@ from nmigen.back.pysim import *
 from heavycomps import uart
 
 
-class Loopback:
+class Loopback(Elaboratable):
     def __init__(self, tuning_word=2**31):
         self.tx = uart.RS232TX(tuning_word)
         self.rx = uart.RS232RX(tuning_word)
diff --git a/heavycomps/heavycomps/uart.py b/heavycomps/heavycomps/uart.py
index 522e3d5..abe80c0 100644
--- a/heavycomps/heavycomps/uart.py
+++ b/heavycomps/heavycomps/uart.py
@@ -2,7 +2,7 @@ from nmigen import *
 from nmigen.lib.cdc import MultiReg
 
 
-class RS232RX:
+class RS232RX(Elaboratable):
     def __init__(self, tuning_word):
         self.rx = Signal()
         self.data = Signal(8)
@@ -58,7 +58,7 @@ class RS232RX:
         return value
 
 
-class RS232TX:
+class RS232TX(Elaboratable):
     def __init__(self, tuning_word):
         self.tx = Signal(reset=1)
         self.data = Signal(8)