diff --git a/cores/minerva.nix b/cores/minerva.nix
index ad2659e..dd7a33a 100644
--- a/cores/minerva.nix
+++ b/cores/minerva.nix
@@ -1,4 +1,5 @@
-{ stdenv, fetchFromGitHub, python3Packages, nmigen, jtagtap }:
+{ stdenv, fetchFromGitHub, python3Packages, nmigen, jtagtap,
+  yosys, symbiyosys, yices }:
 
 python3Packages.buildPythonPackage {
   name = "minerva";
@@ -6,12 +7,15 @@ python3Packages.buildPythonPackage {
   src = fetchFromGitHub {
     owner = "lambdaconcept";
     repo = "minerva";
-    rev = "eefcbd066f2144422b06b398b4651dbd86db52b6";
-    sha256 = "0kv5sgyggic90hf4s3xf2aanwqn1961zhvng6hhzmjsqn1m17rdq";
+    rev = "0518621134dd7a551cac5758d9171a24d0c1578f";
+    sha256 = "1iqddkfmki7wsb3nsrp145d8qfjv3i9fpgkzvh95rq9nz4l7jy6w";
   };
 
   propagatedBuildInputs = [ nmigen jtagtap ];
 
+  checkInputs = [ yosys symbiyosys yices ];
+  checkPhase = "python -m unittest discover minerva.test -v";
+
   meta = with stdenv.lib; {
     description = "A 32-bit RISC-V soft processor";
     homepage    = "https://m-labs.hk/migen";
diff --git a/eda/nmigen-boards.nix b/eda/nmigen-boards.nix
index 20dc394..fdaac62 100644
--- a/eda/nmigen-boards.nix
+++ b/eda/nmigen-boards.nix
@@ -1,15 +1,17 @@
-{ stdenv, fetchFromGitHub, python3Packages, nmigen }:
+{ stdenv, fetchgit, python3Packages, nmigen, git }:
 
 python3Packages.buildPythonPackage {
   name = "nmigen-boards";
+  version = "2019-10-13";
 
-  src = fetchFromGitHub {
-    owner = "m-labs";
-    repo = "nmigen-boards";
-    rev = "6e0cc9d2c9c085912d5350f1f88aaa68af1e25d8";
-    sha256 = "1w3v0hn45hxdmfgl8px0hcc483mq3lzbhrbrgp1nar7f04b2kism";
+  src = fetchgit {
+    url = "https://github.com/m-labs/nmigen-boards";
+    rev = "835c175d7cf9d143aea2c7dbc0c870ede655cfc2";
+    sha256 = "1v0bsy5ccikxmxmsmgq2s14g4dy0df8ka2s6av49833zigjrvh12";
+    leaveDotGit = true;
   };
 
+  nativeBuildInputs = [ python3Packages.setuptools_scm git ];
   propagatedBuildInputs = [ nmigen ];
 
   meta = with stdenv.lib; {
diff --git a/eda/nmigen.nix b/eda/nmigen.nix
index 35f6282..c4dee1e 100644
--- a/eda/nmigen.nix
+++ b/eda/nmigen.nix
@@ -1,17 +1,18 @@
-{ stdenv, fetchFromGitHub, python3Packages, yosys, symbiyosys, yices }:
+{ stdenv, python3Packages, yosys, symbiyosys, yices, git }:
 
-python3Packages.buildPythonPackage {
-  name = "nmigen";
+python3Packages.buildPythonPackage rec {
+  pname = "nmigen";
+  version = "0.1rc1";
 
-  src = fetchFromGitHub {
-    owner = "m-labs";
-    repo = "nmigen";
-    rev = "31c54d32efb9c2851460adc954f5d1fa97800925";
-    sha256 = "1hyjs9pnqp0291pflcxp7yi944r49fgbh2j01r6h0w42q540dj5s";
+  src = python3Packages.fetchPypi {
+    inherit pname version;
+    sha256 = "13vlxn71ackbh8w05fixyxsjypwjginqy9cc5nydlzr3dbhiziw0";
   };
 
-  checkPhase = "PATH=${yosys}/bin:${symbiyosys}/bin:${yices}/bin:$PATH python -m unittest discover nmigen.test -v";
+  checkInputs = [ yosys symbiyosys yices ];
+  checkPhase = "python -m unittest discover nmigen.test -v";
 
+  nativeBuildInputs = [ python3Packages.setuptools_scm git ];
   propagatedBuildInputs = [ python3Packages.bitarray python3Packages.pyvcd python3Packages.jinja2 ];
 
   meta = with stdenv.lib; {
diff --git a/examples/simplesoc_ecp5.py b/examples/simplesoc_ecp5.py
index af8c4a1..0eec864 100644
--- a/examples/simplesoc_ecp5.py
+++ b/examples/simplesoc_ecp5.py
@@ -43,7 +43,7 @@ class Top(Elaboratable):
             cd_sync = ClockDomain(reset_less=True)
             m.domains += cd_sync
             m.d.comb += cd_sync.clk.eq(platform.request("clk100").i)
-            io_user_led = platform.request("user_led").o
+            io_user_led = platform.request("led").o
             io_uart_tx = platform.request("uart").tx.o
 
         counter = Signal(27)
@@ -51,7 +51,7 @@ class Top(Elaboratable):
         m.d.comb += io_user_led.eq(counter[-1])
 
         m.submodules.cpu = cpu = Minerva(with_icache=False, with_dcache=False, with_muldiv=False)
-        m.submodules.ram = ram = wishbone.SRAM(Memory(32, 1024, init=self.firmware))
+        m.submodules.ram = ram = wishbone.SRAM(Memory(width=32, depth=1024, init=self.firmware))
         m.submodules.uart = uart = SimpleWishboneSerial(io_uart_tx, 100e6)
         m.submodules.con = con = wishbone.InterconnectShared(
             [cpu.ibus, cpu.dbus],
diff --git a/overlay.nix b/overlay.nix
index 5361b96..255f1d2 100644
--- a/overlay.nix
+++ b/overlay.nix
@@ -1,25 +1,22 @@
 self: super:
 rec {
-  yosys = super.yosys.overrideAttrs(oa: rec {
+   yosys = super.yosys.overrideAttrs(oa: rec {
     name = "yosys-${version}";
-    version = "2019-07-27";
+    version = "0.9";
     srcs = [
       (super.fetchFromGitHub {
         owner  = "yosyshq";
         repo   = "yosys";
-        rev    = "6538671c84a12114a991d59569eede3e0d368758";
-        sha256 = "1l6v94a9vh9krmfsmd3v8l8xciwf028xvg93qf80s8a75djm7bc3";
+        rev    = "yosys-${version}";
+        sha256 = "0lb9r055h8y1vj2z8gm4ip0v06j5mk7f9zx9gi67kkqb7g4rhjli";
         name   = "yosys";
       })
 
-      # NOTE: the version of abc used here is synchronized with
-      # the one in the yosys Makefile of the version above;
-      # keep them the same for quality purposes.
       (super.fetchFromGitHub {
         owner  = "berkeley-abc";
         repo   = "abc";
-        rev    = "5776ad07e7247993976bffed4802a5737c456782";
-        sha256 = "1la4idmssg44rp6hd63sd5vybvs3vr14yzvwcg03ls37p39cslnl";
+        rev    = "3709744c60696c5e3f4cc123939921ce8107fe04";
+        sha256 = "18a9cjng3qfalq8m9az5ck1y5h4l2pf9ycrvkzs9hn82b1j7vrax";
         name   = "yosys-abc";
       })
     ];