From 88db84cfd7a594e513ba9d0cb2a358bc64cb3864 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Thu, 2 May 2019 12:52:29 +0800
Subject: [PATCH] uart: style

---
 heavycomps/heavycomps/uart.py | 44 ++++++++++++++++++++++-------------
 1 file changed, 28 insertions(+), 16 deletions(-)

diff --git a/heavycomps/heavycomps/uart.py b/heavycomps/heavycomps/uart.py
index 6fb6f23..d4031d3 100644
--- a/heavycomps/heavycomps/uart.py
+++ b/heavycomps/heavycomps/uart.py
@@ -26,12 +26,16 @@ class RS232RX(Elaboratable):
         rx_busy = Signal()
         rx_done = self.stb
         rx_data = self.data
-        m.d.sync += rx_done.eq(0)
-        m.d.sync += rx_r.eq(rx)
+        m.d.sync += [
+            rx_done.eq(0),
+            rx_r.eq(rx)
+        ]
         with m.If(~rx_busy):
             with m.If(~rx & rx_r):  # look for start bit
-                m.d.sync += rx_busy.eq(1)
-                m.d.sync += rx_bitcount.eq(0)
+                m.d.sync += [
+                    rx_busy.eq(1),
+                    rx_bitcount.eq(0)
+                ]
         with m.Else():
             with m.If(uart_clk_rxen):
                 m.d.sync += rx_bitcount.eq(rx_bitcount + 1)
@@ -41,8 +45,10 @@ class RS232RX(Elaboratable):
                 with m.Elif(rx_bitcount == 9):
                     m.d.sync += rx_busy.eq(0)
                     with m.If(rx):  # verify stop bit
-                        m.d.sync += rx_data.eq(rx_reg)
-                        m.d.sync += rx_done.eq(1)
+                        m.d.sync += [
+                            rx_data.eq(rx_reg),
+                            rx_done.eq(1)
+                        ]
                 with m.Else():
                     m.d.sync += rx_reg.eq(Cat(rx_reg[1:], rx))
         with m.If(rx_busy):
@@ -78,23 +84,29 @@ class RS232TX(Elaboratable):
         tx_reg = Signal(8)
         tx_bitcount = Signal(4)
         tx_busy = Signal()
-        m.d.sync += self.ack.eq(0),
+        m.d.sync += self.ack.eq(0)
         with m.If(self.stb & ~tx_busy & ~self.ack):
-            m.d.sync += tx_reg.eq(self.data)
-            m.d.sync += tx_bitcount.eq(0)
-            m.d.sync += tx_busy.eq(1)
-            m.d.sync += self.tx.eq(0)
+            m.d.sync += [
+                tx_reg.eq(self.data),
+                tx_bitcount.eq(0),
+                tx_busy.eq(1),
+                self.tx.eq(0)
+            ]
         with m.Elif(uart_clk_txen & tx_busy):
             m.d.sync += tx_bitcount.eq(tx_bitcount + 1)
             with m.If(tx_bitcount == 8):
                 m.d.sync += self.tx.eq(1)
             with m.Elif(tx_bitcount == 9):
-                m.d.sync += self.tx.eq(1)
-                m.d.sync += tx_busy.eq(0)
-                m.d.sync += self.ack.eq(1),
+                m.d.sync += [
+                    self.tx.eq(1),
+                    tx_busy.eq(0),
+                    self.ack.eq(1)
+                ]
             with m.Else():
-                m.d.sync += self.tx.eq(tx_reg[0])
-                m.d.sync += tx_reg.eq(Cat(tx_reg[1:], 0))
+                m.d.sync += [
+                    self.tx.eq(tx_reg[0]),
+                    tx_reg.eq(Cat(tx_reg[1:], 0))
+                ]
         with m.If(tx_busy):
             m.d.sync += Cat(phase_accumulator_tx, uart_clk_txen).eq(phase_accumulator_tx + self.tuning_word)
         with m.Else():