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simplesoc_ecp5: add blinking LED

This commit is contained in:
Sebastien Bourdeauducq 2019-06-07 23:17:19 +08:00
parent 2cfafcdf20
commit 83ffe66f70
2 changed files with 8 additions and 1 deletions
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2
examples/simplesoc_ecp5.nix
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@ -14,6 +14,8 @@ let
IOBUF PORT "clk100" IO_TYPE=LVDS; IOBUF PORT "clk100" IO_TYPE=LVDS;
LOCATE COMP "serial_tx" SITE "A11"; LOCATE COMP "serial_tx" SITE "A11";
IOBUF PORT "serial_tx" IO_TYPE=LVCMOS33; IOBUF PORT "serial_tx" IO_TYPE=LVCMOS33;
LOCATE COMP "led" SITE "E16";
IOBUF PORT "led" IO_TYPE=LVCMOS25;
EOF EOF
echo -n "--um-45k --speed 8 --package CABGA381" > $out/device echo -n "--um-45k --speed 8 --package CABGA381" > $out/device

7
examples/simplesoc_ecp5.py
View File

@ -29,6 +29,7 @@ class SimpleWishboneSerial(Elaboratable):
class Top(Elaboratable): class Top(Elaboratable):
def __init__(self, firmware): def __init__(self, firmware):
self.clk100 = Signal() self.clk100 = Signal()
self.led = Signal()
self.serial_tx = Signal() self.serial_tx = Signal()
self.firmware = firmware self.firmware = firmware
@ -39,6 +40,10 @@ class Top(Elaboratable):
m.domains += cd_sync m.domains += cd_sync
m.d.comb += cd_sync.clk.eq(self.clk100) m.d.comb += cd_sync.clk.eq(self.clk100)
counter = Signal(27)
m.d.sync += counter.eq(counter + 1)
m.d.comb += self.led.eq(counter[-1])
m.submodules.cpu = cpu = Minerva(with_icache=False, with_dcache=False, with_muldiv=False) m.submodules.cpu = cpu = Minerva(with_icache=False, with_dcache=False, with_muldiv=False)
m.submodules.ram = ram = wishbone.SRAM(Memory(32, 1024, init=self.firmware)) m.submodules.ram = ram = wishbone.SRAM(Memory(32, 1024, init=self.firmware))
m.submodules.uart = uart = SimpleWishboneSerial(self.serial_tx, 100e6) m.submodules.uart = uart = SimpleWishboneSerial(self.serial_tx, 100e6)
@ -73,7 +78,7 @@ def main():
top = Top(firmware) top = Top(firmware)
output = rtlil.convert(Fragment.get(top, None), output = rtlil.convert(Fragment.get(top, None),
ports=(top.clk100, top.serial_tx)) ports=(top.clk100, top.led, top.serial_tx))
with open(args.output_file, "w") as f: with open(args.output_file, "w") as f:
f.write(output) f.write(output)