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simplesoc_ecp5: add simulation

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This commit is contained in:
Sebastien Bourdeauducq 2019-06-08 17:30:49 +08:00
parent 83ffe66f70
commit 75e9310097
1 changed files with 22 additions and 12 deletions
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18
examples/simplesoc_ecp5.py
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@ -2,7 +2,7 @@ import argparse
import struct
from nmigen import *
from nmigen.back import rtlil
from nmigen.back import rtlil, pysim
from heavycomps import uart, wishbone
from minerva.core import Minerva
@ -27,7 +27,8 @@ class SimpleWishboneSerial(Elaboratable):
class Top(Elaboratable):
def __init__(self, firmware):
def __init__(self, firmware, create_clock):
if create_clock:
self.clk100 = Signal()
self.led = Signal()
self.serial_tx = Signal()
@ -36,6 +37,7 @@ class Top(Elaboratable):
def elaborate(self, platform):
m = Module()
if hasattr(self, "clk100"):
cd_sync = ClockDomain(reset_less=True)
m.domains += cd_sync
m.d.comb += cd_sync.clk.eq(self.clk100)
@ -64,19 +66,27 @@ def read_firmware(file):
word = f.read(4)
if len(word) < 4:
break
firmware.append(struct.unpack(">I", word)[0])
firmware.append(struct.unpack("<I", word)[0])
return firmware
def main():
parser = argparse.ArgumentParser()
parser.add_argument("--simulate", action="store_true")
parser.add_argument("firmware_bin")
parser.add_argument("output_file")
args = parser.parse_args()
firmware = read_firmware(args.firmware_bin)
top = Top(firmware, create_clock=not args.simulate)
top = Top(firmware)
if args.simulate:
with pysim.Simulator(top,
vcd_file=open(args.output_file + ".vcd", "w"),
gtkw_file=open(args.output_file + ".gtkw", "w")) as sim:
sim.add_clock(1e-6)
sim.run_until(100e-6, run_passive=True)
else:
output = rtlil.convert(Fragment.get(top, None),
ports=(top.clk100, top.led, top.serial_tx))
with open(args.output_file, "w") as f: