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gitea doesn't like rst

This commit is contained in:
Sebastien Bourdeauducq 2019-06-10 14:51:07 +08:00
parent 40f869632b
commit 630048ae5f
2 changed files with 21 additions and 18 deletions
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26
README.rst → README.md
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@ -13,10 +13,10 @@ Use nixpkgs unstable (known to work with ae71c13). Check https://nixbld.m-labs.h
Optional: set up the M-Labs key and binary substituter for Nix (otherwise Nix will recompile LLVM, rustc, etc. on your machine). Optional: set up the M-Labs key and binary substituter for Nix (otherwise Nix will recompile LLVM, rustc, etc. on your machine).
Create the file ``~/.config/nix/nix.conf`` with the following contents: Create the file ``~/.config/nix/nix.conf`` with the following contents:
:: ```
substituters = https://cache.nixos.org https://nixbld.m-labs.hk
substituters = https://cache.nixos.org https://nixbld.m-labs.hk trusted-public-keys = cache.nixos.org-1:6NCHdD59X431o0gWypbMrAURkbJ16ZPMQFGspcDShjY= nixbld.m-labs.hk-1:5aSRVA5b320xbNvu30tqxVPXpld73bhtOeH6uAjRyHc=
trusted-public-keys = cache.nixos.org-1:6NCHdD59X431o0gWypbMrAURkbJ16ZPMQFGspcDShjY= nixbld.m-labs.hk-1:5aSRVA5b320xbNvu30tqxVPXpld73bhtOeH6uAjRyHc= ```
Run ``nix-build -A simplesoc_ecp5 release.nix`` Run ``nix-build -A simplesoc_ecp5 release.nix``
@ -24,15 +24,15 @@ Bypass the ispCLOCK device using the jumpers on your board.
Create a ``versa.cfg`` file with: Create a ``versa.cfg`` file with:
:: ```
interface ftdi
interface ftdi ftdi_vid_pid 0x0403 0x6010
ftdi_vid_pid 0x0403 0x6010 ftdi_channel 0
ftdi_channel 0 ftdi_layout_init 0xfff8 0xfffb
ftdi_layout_init 0xfff8 0xfffb reset_config none
reset_config none adapter_khz 5000
adapter_khz 5000 jtag newtap ecp5 tap -irlen 8 -expected-id 0x01112043
jtag newtap ecp5 tap -irlen 8 -expected-id 0x01112043 ```
Load the bitstream ``openocd -f versa.cfg -c "transport select jtag; init; svf result/top.svf; exit"``. Load the bitstream ``openocd -f versa.cfg -c "transport select jtag; init; svf result/top.svf; exit"``.

13
firmware/src/main.rs
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@ -6,13 +6,16 @@ extern crate panic_halt;
use riscv_rt::entry; use riscv_rt::entry;
#[entry] fn print(string: &str) {
fn main() -> ! { for c in string.chars() {
let foo = "hello world\n";
loop {
for c in foo.chars() {
let mem = 0x00400000 as *mut u8; let mem = 0x00400000 as *mut u8;
unsafe { *mem = c as u8 } unsafe { *mem = c as u8 }
} }
}
#[entry]
fn main() -> ! {
loop {
print("hello2");
} }
} }