218 lines
7.9 KiB
Rust
218 lines
7.9 KiB
Rust
use embedded_hal::{blocking::spi::Transfer, digital::v2::OutputPin};
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pub mod interfaces {
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use embedded_hal::spi;
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/// Must use SPI mode cpol=0, cpha=0
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pub const SPI_MODE: spi::Mode = spi::Mode {
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polarity: spi::Polarity::IdleLow,
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phase: spi::Phase::CaptureOnFirstTransition,
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};
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/// Max freq = 14 MHz
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pub const SPI_CLOCK_FREQ: u32 = 14_000_000;
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}
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pub mod opcodes {
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/// 1-byte Instructions
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pub const SETETHRST: u8 = 0b1100_1010;
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pub const SETPKTDEC: u8 = 0b1100_1100;
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pub const SETTXRTS: u8 = 0b1101_0100;
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pub const ENABLERX: u8 = 0b1110_1000;
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/// 3-byte Instructions
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pub const WRXRDPT: u8 = 0b0110_0100; // 8-bit opcode followed by data
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pub const RRXRDPT: u8 = 0b0110_0110; // 8-bit opcode followed by data
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pub const WGPWRPT: u8 = 0b0110_1100; // 8-bit opcode followed by data
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pub const RGPWRPT: u8 = 0b0110_1110; // 8-bit opcode followed by data
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/// N-byte Instructions
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pub const RCRU: u8 = 0b0010_0000;
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pub const WCRU: u8 = 0b0010_0010;
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pub const RRXDATA: u8 = 0b0010_1100; // 8-bit opcode followed by data
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pub const WGPDATA: u8 = 0b0010_1010; // 8-bit opcode followed by data
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}
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pub mod addrs {
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/// SPI Register Mapping
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/// Note: PSP interface use different address mapping
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// SPI Init Reset Registers
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pub const EUDAST: u8 = 0x16; // 16-bit data
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pub const ESTAT: u8 = 0x1a; // 16-bit data
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pub const ECON2: u8 = 0x6e; // 16-bit data
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//
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pub const ERXFCON: u8 = 0x34; // 16-bit data
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//
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pub const MAADR3: u8 = 0x60; // 16-bit data
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pub const MAADR2: u8 = 0x62; // 16-bit data
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pub const MAADR1: u8 = 0x64; // 16-bit data
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// RX Registers
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pub const ERXRDPT: u8 = 0x8a; // 16-bit data
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pub const ERXST: u8 = 0x04; // 16-bit data
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pub const ERXTAIL: u8 = 0x06; // 16-bit data
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pub const EIR: u8 = 0x1c; // 16-bit data
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pub const ECON1: u8 = 0x1e; // 16-bit data
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pub const MAMXFL: u8 = 0x4a; // 16-bit data
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// TX Registers
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pub const EGPWRPT: u8 = 0x88; // 16-bit data
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pub const ETXST: u8 = 0x00; // 16-bit data
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pub const ETXSTAT: u8 = 0x12; // 16-bit data
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pub const ETXLEN: u8 = 0x02; // 16-bit data
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}
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/// Struct for SPI I/O interface on ENC424J600
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/// Note: stm32f4xx_hal::spi's pins include: SCK, MISO, MOSI
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pub struct SpiPort<SPI: Transfer<u8>, NSS: OutputPin> {
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spi: SPI,
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nss: NSS,
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#[cfg(feature = "cortex-m-cpu")]
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cpu_freq_mhz: f32,
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}
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pub enum Error {
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OpcodeError,
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TransferError,
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}
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#[allow(unused_must_use)]
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impl<SPI: Transfer<u8>, NSS: OutputPin> SpiPort<SPI, NSS> {
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// TODO: return as Result()
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pub fn new(spi: SPI, mut nss: NSS) -> Self {
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nss.set_high();
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SpiPort {
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spi,
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nss,
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#[cfg(feature = "cortex-m-cpu")]
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cpu_freq_mhz: 0.,
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}
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}
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#[cfg(feature = "cortex-m-cpu")]
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pub fn cpu_freq_mhz(mut self, freq: u32) -> Self {
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self.cpu_freq_mhz = freq as f32;
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self
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}
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pub fn read_reg_8b(&mut self, addr: u8) -> Result<u8, Error> {
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// Using RCRU instruction to read using unbanked (full) address
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let mut buf: [u8; 4] = [0; 4];
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buf[1] = addr;
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self.rw_n(&mut buf, opcodes::RCRU, 2)?;
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Ok(buf[2])
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}
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pub fn read_reg_16b(&mut self, lo_addr: u8) -> Result<u16, Error> {
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// Unless the register can be written with specific opcode,
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// use WCRU instruction to write using unbanked (full) address
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let mut buf: [u8; 4] = [0; 4];
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let mut data_offset = 0; // number of bytes separating
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// actual data from opcode
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match lo_addr {
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addrs::ERXRDPT | addrs::EGPWRPT => {}
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_ => {
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buf[1] = lo_addr;
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data_offset = 1;
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}
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}
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self.rw_n(
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&mut buf,
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match lo_addr {
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addrs::ERXRDPT => opcodes::RRXRDPT,
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addrs::EGPWRPT => opcodes::RGPWRPT,
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_ => opcodes::RCRU,
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},
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2 + data_offset, // extra 8-bit lo_addr before data
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)?;
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Ok(buf[data_offset + 1] as u16 | (buf[data_offset + 2] as u16) << 8)
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}
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// Currently requires manual slicing (buf[1..]) for the data read back
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pub fn read_rxdat<'a>(&mut self, buf: &'a mut [u8], data_length: usize) -> Result<(), Error> {
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self.rw_n(buf, opcodes::RRXDATA, data_length)
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}
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// Currently requires actual data to be stored in buf[1..] instead of buf[0..]
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// TODO: Maybe better naming?
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pub fn write_txdat<'a>(&mut self, buf: &'a mut [u8], data_length: usize) -> Result<(), Error> {
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self.rw_n(buf, opcodes::WGPDATA, data_length)
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}
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pub fn write_reg_8b(&mut self, addr: u8, data: u8) -> Result<(), Error> {
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// Using WCRU instruction to write using unbanked (full) address
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let mut buf: [u8; 3] = [0; 3];
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buf[1] = addr;
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buf[2] = data;
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self.rw_n(&mut buf, opcodes::WCRU, 2)
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}
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pub fn write_reg_16b(&mut self, lo_addr: u8, data: u16) -> Result<(), Error> {
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// Unless the register can be written with specific opcode,
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// use WCRU instruction to write using unbanked (full) address
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let mut buf: [u8; 4] = [0; 4];
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let mut data_offset = 0; // number of bytes separating
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// actual data from opcode
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match lo_addr {
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addrs::ERXRDPT | addrs::EGPWRPT => {}
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_ => {
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buf[1] = lo_addr;
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data_offset = 1;
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}
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}
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buf[1 + data_offset] = data as u8;
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buf[2 + data_offset] = (data >> 8) as u8;
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self.rw_n(
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&mut buf,
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match lo_addr {
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addrs::ERXRDPT => opcodes::WRXRDPT,
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addrs::EGPWRPT => opcodes::WGPWRPT,
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_ => opcodes::WCRU,
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},
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2 + data_offset, // extra 8-bit lo_addr before data
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)
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}
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pub fn send_opcode(&mut self, opcode: u8) -> Result<(), Error> {
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match opcode {
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opcodes::SETETHRST | opcodes::SETPKTDEC | opcodes::SETTXRTS | opcodes::ENABLERX => {
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let mut buf: [u8; 1] = [0];
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self.rw_n(&mut buf, opcode, 0)
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}
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_ => Err(Error::OpcodeError),
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}
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}
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// TODO: Actual data should start from buf[0], not buf[1]
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// Completes an SPI transfer for reading data to the given buffer,
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// or writing data from the buffer.
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// It sends an 8-bit instruction, followed by either
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// receiving or sending n*8-bit data.
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// The slice of buffer provided must begin with the 8-bit instruction.
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// If n = 0, the transfer will only involve sending the instruction.
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fn rw_n<'a>(&mut self, buf: &'a mut [u8], opcode: u8, data_length: usize) -> Result<(), Error> {
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assert!(buf.len() > data_length);
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// Enable chip select
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self.nss.set_low();
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// >=50ns min. CS_n setup time
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#[cfg(feature = "cortex-m-cpu")]
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cortex_m::asm::delay((0.05 * (self.cpu_freq_mhz + 1.)) as u32);
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// Start writing to SLAVE
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buf[0] = opcode;
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let result = self.spi.transfer(&mut buf[..data_length + 1]);
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match opcode {
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opcodes::RCRU | opcodes::WCRU | opcodes::RRXDATA | opcodes::WGPDATA => {
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// Disable chip select
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// >=50ns min. CS_n hold time
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#[cfg(feature = "cortex-m-cpu")]
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cortex_m::asm::delay((0.05 * (self.cpu_freq_mhz + 1.)) as u32);
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self.nss.set_high();
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// >=20ns min. CS_n disable time
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#[cfg(feature = "cortex-m-cpu")]
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cortex_m::asm::delay((0.02 * (self.cpu_freq_mhz + 1.)) as u32);
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}
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_ => {}
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}
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match result {
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Ok(_) => Ok(()),
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// TODO: Maybe too naive?
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Err(_) => Err(Error::TransferError),
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}
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}
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}
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