Dimitris

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• Joined on 2024-11-05

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urukul-pld

Python 0 0

CPLD/FPGA gateware on Urukul. Forked from https://github.com/quartiq/urukul

Updated 2025-05-15 22:39:44 +08:00

artiq-zynq

Rust 0 0

ARTIQ Zynq-based core device support

Updated 2025-02-08 12:58:20 +08:00