forked from M-Labs/nac3
core: Remove emit_llvm from CodeGenLLVMOptions
We instead output an LLVM bitcode file when the option is specified on the command-line.
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ab2360d7a0
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@ -916,7 +916,6 @@ impl Nac3 {
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llvm_options: CodeGenLLVMOptions {
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llvm_options: CodeGenLLVMOptions {
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opt_level: OptimizationLevel::Default,
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opt_level: OptimizationLevel::Default,
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target: Nac3::get_llvm_target_options(isa),
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target: Nac3::get_llvm_target_options(isa),
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emit_llvm: false,
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}
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}
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})
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})
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}
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}
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@ -61,9 +61,6 @@ pub struct CodeGenLLVMOptions {
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/// Options related to the target machine.
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/// Options related to the target machine.
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pub target: CodeGenTargetMachineOptions,
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pub target: CodeGenTargetMachineOptions,
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/// Whether to output the LLVM IR after generation is complete.
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pub emit_llvm: bool,
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}
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}
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/// Additional options for code generation for the target machine.
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/// Additional options for code generation for the target machine.
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@ -339,11 +336,6 @@ impl WorkerRegistry {
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err.to_string());
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err.to_string());
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}
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}
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if self.llvm_options.emit_llvm {
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println!("LLVM IR for {}\n{}", module.get_name().to_str().unwrap(), module.to_string());
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println!();
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}
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f.run(&module);
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f.run(&module);
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let mut lock = self.task_count.lock();
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let mut lock = self.task_count.lock();
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*lock += 1;
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*lock += 1;
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@ -222,7 +222,6 @@ fn test_primitives() {
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let llvm_options = CodeGenLLVMOptions {
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let llvm_options = CodeGenLLVMOptions {
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opt_level: OptimizationLevel::Default,
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opt_level: OptimizationLevel::Default,
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target: CodeGenTargetMachineOptions::from_host_triple(),
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target: CodeGenTargetMachineOptions::from_host_triple(),
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emit_llvm: false,
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};
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};
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let (registry, handles) = WorkerRegistry::create_workers(
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let (registry, handles) = WorkerRegistry::create_workers(
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threads,
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threads,
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@ -413,7 +412,6 @@ fn test_simple_call() {
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let llvm_options = CodeGenLLVMOptions {
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let llvm_options = CodeGenLLVMOptions {
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opt_level: OptimizationLevel::Default,
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opt_level: OptimizationLevel::Default,
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target: CodeGenTargetMachineOptions::from_host_triple(),
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target: CodeGenTargetMachineOptions::from_host_triple(),
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emit_llvm: false,
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};
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};
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let (registry, handles) = WorkerRegistry::create_workers(
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let (registry, handles) = WorkerRegistry::create_workers(
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threads,
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threads,
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@ -305,7 +305,6 @@ fn main() {
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features: target_features,
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features: target_features,
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..host_target_machine
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..host_target_machine
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},
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},
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emit_llvm,
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};
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};
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let task = CodeGenTask {
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let task = CodeGenTask {
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@ -340,11 +339,19 @@ fn main() {
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let main = context
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let main = context
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.create_module_from_ir(MemoryBuffer::create_from_memory_range(&buffers[0], "main"))
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.create_module_from_ir(MemoryBuffer::create_from_memory_range(&buffers[0], "main"))
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.unwrap();
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.unwrap();
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for buffer in buffers.iter().skip(1) {
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if emit_llvm {
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main.write_bitcode_to_path(Path::new("main.bc"));
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}
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for (idx, buffer) in buffers.iter().skip(1).enumerate() {
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let other = context
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let other = context
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.create_module_from_ir(MemoryBuffer::create_from_memory_range(buffer, "main"))
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.create_module_from_ir(MemoryBuffer::create_from_memory_range(buffer, "main"))
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.unwrap();
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.unwrap();
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if emit_llvm {
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other.write_bitcode_to_path(Path::new(&format!("module{}.bc", idx)));
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}
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main.link_in_module(other).unwrap();
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main.link_in_module(other).unwrap();
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}
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}
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main.link_in_module(load_irrt(&context)).unwrap();
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main.link_in_module(load_irrt(&context)).unwrap();
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